Altera POS-PHY Level 4 IP Core Manual do Utilizador descarregar pdf (Página 110)

A–4 Appendix A: Start-Up Sequence

Troubleshooting

POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

1. The PLL locked signal is not asserted or toggles. Ensure that the input clock jitter is

within the PLL jitter requirements. In some cases, if the PLL locked signal toggles,

the PLL must be reset. If so, perform the appropriate steps listed in Table A–1 on

page A–2. Refer to your PLL’s documentation for further information.

2. Data channel does not sync. This problem can be detected when

stat_rd_rdat_sync

remains low or toggles. The following tips may prove useful:

■ Ensure all resets are released.

■ Ensure all clocks are up, and measure clock frequencies.

■ Ensure training patterns are received.

3. Data channel syncs but only training patterns are received. This problem can be

detected when

stat_rd_rdat_sync

goes high, but no data is received, and

stat_rd_tp_flag

toggles. The following tips may prove useful:

■ For 128-bit receiver variations, ensure that the

rxsys_clk

rdint_clk

ratio is

set according to the receive clock setting in Table C–1 on page C–1.

■ Ensure that the calendar length and calendar multiplier are set to the same

values in both devices.

■ Verify timing requirements for the status channel

■ Select the clock edge that drives or samples the clock with

ctl_ts_statedge

and

ctl_rs_statedge

■ Verify t

for the

rsclk

and

rstat

pins in the receiver IP core. The ALTDDIO IP

core keeps on-chip skew to a minimum.

■ Verify board skew for

rsclk

rstat

■ Verify the setup and hold times for

tstat

tsclk

in the transmit IP core. The

ALTDDIO IP core keeps on-chip skew to a minimum.

■ Verify that

tsclk

is operating at the correct frequency.

4. Data channel syncs but

stat_ry_disabled

goes high or toggles. The rx_stat_phy

FIFO buffer may be underflowing or overflowing, due to incorrect configuration.

For guidance, refer to the relevant comments in <variation name>_rx_core.v HDL

file (

rx_stat_phy

section, setting the thresholds).

5. Receive IP core detects DIP-4 errors during normal transmission. The following

tips may prove useful:

■ The receiver IP core (non-DPA variations) assume that the data is edge aligned.

The alignment can be changed at the receiver and transmitter. It is easier to

change the receiver by specifying a different alignment using the

INCLOCK_DATA_ALIGNMENT

parameter of the ALTLVDS IP core. In the

transmitter, the

tdclk

can be driven by a PLL clock output instead of a SERDES

1 2 ... 105 106 107 108 109 110 111 112 113 114 115 ... 141 142

Comentários a estes Manuais

Sem comentários

Altera POS-PHY Level 4 IP Core Manual do Utilizador Página 110

Comentários a estes Manuais

Manuais e produtos relacionados com Instrumentos de medida Altera POS-PHY Level 4 IP Core