Altera POS-PHY Level 4 IP Core Manual do Utilizador descarregar pdf (Página 7)

Chapter 1: About This IP Core 1–5

IP Core Verification

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide

In this version of the POS-PHY Level 4 IP core, the Avalon-MM module is a discrete

unit that is instantiated with the parameter editor, when Asymmetric Port Support is

turned on.

f For further information on this interface, refer to the Avalon Interface Specifications.

IP Core Verification

The POS-PHY Level 4 IP core has been rigorously tested and verified in hardware for

different platforms and environments. Each environment has individual test suites

that are designed to cover the following five categories of testability:

■ Sanity

■ Flow Control

■ Error Management

■ Performance

■ Stress

These test suites contain several testbenches that are grouped and focused on testing

specific features of the POS-PHY Level 4 IP core. These individual testbenches set

unique parameters for each specific feature test.

Results of the hardware verification tests are gathered in I-tested reports available for

different ASSP devices. For example, SPI-4.2 Interoperability with PMC-Sierra’s S/UNI

9953 and SPI-4.2 Interoperability with PMC-Sierra’s S/UNI 10×GE (PM3388).

f For these reports, contact your local Altera sales representative or FAE.

Performance and Resource Utilization

Table 1–4 lists the resources and internal speeds for variations using the shared buffer

with embedded addressing mode.

Table 1–5 lists the resources and internal speeds for a selection of variations using the

individual buffers mode.

All of the results use the Quartus II software version 8.1 for the following devices:

■ Stratix IV GX (EP4SGX70DF29C3 and EP4SGX230DF29C3ES)

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Altera POS-PHY Level 4 IP Core Manual do Utilizador Página 7