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Appendix A: Parameters A–3
Parameter Lists
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
Clocking Options
Table A–3 lists the parameters modified by settings on the Clocking Options tab of
the IP Toolbench wizard.
.
Advanced Settings
Table A–4 lists parameters modified by settings on the Advanced Settings tab of the
IP Toolbench wizard.
Table A–3. Clocking Options Parameters
Parameter Default
Available
Setting(s) Description
CLKDMN 3 1, 2, 3 This parameter selects the clocking option for the HyperTransport
MegaCore function.
Values have the following meanings:
1 – Shared Rx/Tx/Ref Clock option
2 – Shared Ref/Tx Clock option
3 – Shared Rx/Tx Clock option
Refer to “Clocking Options” on page 3–7 for a discussion of these
options.
HT_RX_CLK_PERIOD 2500 2000, 2500,
3333, 5000
HT Rx link clock period in picoseconds. This parameter sets the
Rx PLL parameters for the correct Rx frequency. Set this
parameter to the highest operating frequency. The PLL still locks
at the slower frequencies.
HT_TX_CLK_PERIOD 2500 2000, 2500,
3333, 5000
HT Tx link clock period in picoseconds. This parameter sets the
Tx PLL parameters for the correct Tx frequency. Set this
parameter to the highest operating frequency. The PLL still locks
at the slower frequencies.
This parameter is only used in the Shared Ref/Tx Clock option. In
the other clock options, the Tx PLL is shared with the Rx PLL.
Table A–4. Advanced Settings Parameters (Part 1 of 2)
Parameter Default
Available
Setting(s) Description
RxPBufNum 8 8, 16 Selects either 8 or 16 Rx posted buffers. Selecting 16 Rx posted
buffers may increase throughput but also consumes additional
resources.
RxNpBufNum 4 4, 8 Selects either 4 or 8 Rx non-posted buffers. Selecting 8 Rx
non-posted buffers may increase performance but also consumes
additional resources.
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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