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Chapter 3: Specifications 3–19
HyperTransport MegaCore Function Specification
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
Rx Buffer Ordering
The circular Rx buffers allow the local-side application to read packets in the order in
which they were received from the link. This implementation satisfies the HT
specification ordering requirements within the same virtual channel and between the
different channels.
If a response or non-posted packet with the PassPW bit reset is received, the HT
specification requires that the packet not be processed until after the preceding posted
packet is processed. The response and non-posted buffers are designed to enforce this
requirement. For example, if a response packet with PassPW bit reset is received, the
MegaCore function cannot read that packet from the response buffer until all
preceeding posted packets are read from the Rx posted buffers. In this case, RxRDav is
not asserted, and if the user interface asserts RxREna, RxRVal is deasserted to
indicate invalid data until the preceeding posted packets are read from the posted
buffer.
If PassPW is set on a received non-posted or response packet, the packets can be read
out of the Rx buffers as soon as they are head of queue in their virtual channel,
independent of any posted requests that may have arrived earlier.
1 If a response packet with the PassPW bit set is received after another response packet
with the PassPW bit reset, you cannot read the packet with the PassPW bit set until
the previous one with the PassPW bit reset is read from the buffer. The same is true for
non-posted packets.
Table 3–6 shows the Rx buffer ordering rules implemented by the HyperTransport
MegaCore function.
Table 3–6. Rx Buffer Ordering
Row Pass Column Posted Request Non-Posted Request Response
Request
Type PassPW
Specification
(1)
MegaCore
Function
Specification
(1)
MegaCore
Function
Specification
(1)
MegaCore
Function
Posted 1 Yes/No No Yes Yes (2) Yes Yes (2)
0No
Non-posted 1 Yes/No Yes (2) Yes/No No Yes/No Yes (2)
0No No
Response 1 Yes/No Yes (2) Yes Yes (2) Yes/No No
0No No
Notes to Table 3–6:
(1) This column indicates the requirements as specified by the HyperTransport I/O Link Specification Revision 1.03.
No—The row request type may not pass the column request type.
Yes—The row request type must be allowed to pass the column request type to avoid deadlock conditions.
Yes/No—The row request type may pass the column request type but there is no requirement to do so.
(2) A “Yes” indicates that the MegaCore function allows the row to pass the column if the user application asserts the row Ena_i before the column
Ena_i.
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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