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3–26 Chapter 3: Specifications
HyperTransport MegaCore Function Specification
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
Preliminary
Tx Command/Data Buffer Interface Timing Diagrams
Figure 3–14 shows a 32-byte read response being transferred to the HyperTransport
MegaCore function across the Tx interface.
Figure 3–15 shows a 28-byte write being transferred to the HyperTransport MegaCore
function across the Tx Interface. The user logic inserts a wait state during the transfer.
Figure 3–14. Single 32-Byte Read Response across Tx Interface, No Wait States Timing Diagram
Notes to Figure 3–14:
(1) In this example, Dav_o starts out low. The clock cycle after Dav_o is asserted, the user application asserts DatEna_i. In other cases, Dav_o
may be high for many clock cycles and the user application does not assert DatEna_i until it has data available.
(2) Dav_o goes low in this example to indicate the TxResp buffer is full and cannot accept a subsequent command. However, the user application
still asserts DatEna_i to complete the current command.
(3) Some time later Dav_o is reasserted, indicating another command can be accepted.
(4) Dat_o[63:32] is not valid in this example because the command is only a read response.
234567 910
RefClk
Dav_o
81
DatEna_i
Dat_i[31:0]
Dat_i[63:32]
Sop_i
Eop_i
WrRjct_o
Mty_i[2:0]
11
RdResp DW0 DW2 DW4 DW6
DW1 DW3 DW5 DW7
0b000
(2) (3)
(4)
(1)
Figure 3–15. User Wait States on the Tx Interface Timing Diagram
Notes to Figure 3–15:
(1) In this example, Dav_o is high for many clock cycles and the user application asserts DatEna_i when it has data available.
(2) Dav_o goes low in this example to indicate the TxResp buffer is full and cannot accept a subsequent command. However, the user application
still asserts DatEna_i to complete the current command.
(3) Some time later Dav_o is reasserted, indicating another command can be accepted.
(4) The user inserts a wait state in the transfer by deasserting DatEna_i; the other inputs are Don’t Cares in this clock cycle.
(5) Dat_i[63:32] is not valid because this example is only seven double-words.
234567 910
RefClk
Dav_o
81
DatEna_i
Dat_i[31:0]
Dat_i[63:32]
Sop_i
Eop_i
WrRjct_o
Mty_i[2:0]
11
(1)
Write DW0 DW2 DW4 DW6
DW1 DW3 DW5
(5)
0b000
(2) (3)
Addr[39:8]
(4)
(4)
0b100
(4)
(4)
(4)
0b000
(4)
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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