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3–18 Chapter 3: Specifications
HyperTransport MegaCore Function Specification
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
Preliminary
Sop_o Output Start of packet. This signal indicates the start of packet. When Sop_o is high, start of
packet is present on Dat_o[63:0] and is aligned to the least significant byte. Sop_o
is qualified with the Val_o signal. If Val_o is low, Sop_o must be ignored.
Eop_o Output End of packet. This signal indicates the end of packet. When Eop_o is high, end of data
packet is present on Dat_o[63:0] and is aligned to the least significant byte. Eop_o
is qualified with the Val_o signal. If Val_o is low, Eop_o must be ignored.
Val_o Output Data valid. This signal indicates that the data driven on Dat_o[63:0] is valid. Val_o
is updated on every RefClk edge at which Ena_i is sampled asserted, and holds its
current value along with the Dat_o bus when Ena_i is sampled deasserted. When
Val_o is asserted, the Atlantic data interface signals are valid. When Val_o is
deasserted, the Atlantic data interface signals are invalid and must be ignored. To
determine whether new data has been received, the master must qualify the Val_o
signal with the previous state of the Ena_i signal.
The Rx buffers always provide all words of a packet on consecutive cycles (Val_o
asserted) as long as Ena_i remains asserted during the packet. In addition, if Ena_i is
asserted on the last word of a packet and the next packet is available, the next packet
starts on the cycle immediately after the current packet completes.
Dav_o Output Data available. This signal functions as the Dav signal in the Atlantic interface
specification with the HyperTransport MegaCore function as the slave source. If Dav_o
is high, the buffer has at least one command/data packet available to be read. If this
signal is not asserted, it indicates that there are no valid packets available to be read.
Ena_i Input Data transfer enable. This signal functions as the Ena signal in the Atlantic interface
specification with the HyperTransport MegaCore function as a slave source. Ena_i is
driven by the interface master and is used to control the flow of data across the interface.
Ena_i behaves as a read enable from master to slave. When the slave observes Ena_i
asserted on the RefClk rising edge, it drives, on the following RefClk rising edge, the
Atlantic data interface signals and asserts Val_o. The master captures the data interface
signals on the following RefClk rising edge.
BarHit_o[2:0] Output BAR match indication. For the Rx posted and Rx non-posted interfaces, this bus indicates
which BAR the packet matched.
00
0 32-bit BAR0 or 64-bit BAR01
001 32-bit BAR1
010 32-bit BAR2 or 64-bit BAR23
011 32-bit BAR3
100 32-bit BAR4 or 64-bit BAR45
101 32-bit BAR5
110 Not used
111 Non-address packet
This bus is valid only when Val_o and Sop_o are asserted.
Because responses are not claimed due to address matches, this bus does not exist in
the response buffer interface.
Table 3–5. Rx Command/Data Buffer Interface Signals (Part 2 of 2)
Signal Name Direction Description
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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