Altera HyperTransport MegaCore Function Manual do Utilizador Página 56
- Página / 76
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
3–30 Chapter 3: Specifications
HyperTransport MegaCore Function Specification
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
Preliminary
During normal operation of the HyperTransport link, clocks may change from the
initial 200 MHz frequency to a faster frequency. If the RxClk_i input to the function
stops during this change, the Rx PLL must be reset. The HyperTransport interface
does not provide sufficient indication to directly generate the PLL reset for this
situation. However, a Verilog HDL reference design that generates the
HyperTransport Rx PLL reset at the appropriate time is installed with the
HyperTransport MegaCore function.
f The Verilog HDL reference design code that generates the HT Rx PLL reset at the
appropriate time can be found in your Altera MegaCore IP library installation at
<path>/ht/example/pll_reset/ht_with_pll_reset.v
The RxPllAreset_i and TxPllAreset_i inputs can be tied low to provide the
PLL behavior that was present in HyperTransport MegaCore function v1.3.0 and
earlier.
CSR Interface Signals
All required status information in the CSR module is provided to the local side
through the signals shown in Table 3–10.
Table 3–10. CSR Interface Signals
Signal Name Direction Description
CsrCmdReg[15:0] Output Command register.
CsrStatReg[15:0] Output Status register.
CsrCapReg[15:0] Output Capability command register.
CsrCapLnk0CtrlReg[15:0] Output Capability link 0 control register.
CsrCapLnk1CtrlReg[15:0] Output Capability link 1 control register.
CsrCapLnk0CfgReg[15:0] Output Capability link 0 configuration register.
CsrCapLnk1CfgReg[15:0] Output Capability link 1 configuration register.
CsrCapFtrReg[7:0] Output Capability feature register.
CsrCapLnk0ErrReg[3:0] Output Capability link 0 error register.
CsrCapLnk1ErrReg[3:0] Output Capability link 1 error register.
CsrCapErrHndlngReg[15:0] Output Capability error handling register.
Bar0Reg[31:0] Output Base address register 0.
Bar1Reg[31:0] Output Base address register 1.
Bar2Reg[31:0] Output Base address register 2.
Bar3Reg[31:0] Output Base address register 3.
Bar4Reg[31:0] Output Base address register 4.
Bar5Reg[31:0] Output Base address register 5.
RespErr Input The user application logic asserts this signal to indicate that an
unexpected response was received. Asserting this signal causes the
appropriate CSR bit to be set.
SignaledTabrt Input The user application logic asserts this signal to indicate that a target
abort was signaled (the target issued a response with a non-NXA error).
Asserting this signal causes the appropriate CSR bit to be set.
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
Manuais e produtos relacionados com Instrumentos de medida Altera HyperTransport MegaCore Function
Instrumentos de medida Altera High-Speed Development Kit, Stratix GX Edition Manual do Utilizador
(140 páginas)
(140 páginas)
Instrumentos de medida Altera Internal Memory (RAM and ROM) IP Core Manual do Utilizador
(57 páginas)
(57 páginas)
Instrumentos de medida Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manual do Utilizador
(196 páginas)
(196 páginas)
Instrumentos de medida Altera JNEye Manual do Utilizador
(194 páginas)
(194 páginas)
Instrumentos de medida Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Manual do Utilizador
(413 páginas)
(413 páginas)
Instrumentos de medida Altera Mentor Verification IP Altera Edition AMBA AXI4-St Manual do Utilizador
(231 páginas)
(231 páginas)
Instrumentos de medida Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Manual do Utilizador
(783 páginas)
(783 páginas)
Instrumentos de medida Altera PCI Development Kit, Cyclone II Edition Getting St Manual do Utilizador
(40 páginas)
(40 páginas)
© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.025 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais