Altera Arria V GX FPGA Development Board Manual do Utilizador descarregar pdf (Página 52)

2–42 Chapter 2: Board Components

Components and Interfaces

Arria V GX FPGA Development Board November 2013 Altera Corporation

Reference Manual

HSMC

The development board contains two HSMC interfaces—port A on device 1 and

port B on device 2. HSMC port A and port B interfaces support both single-ended and

differential signaling. This physical interface provides four channels of

6.5536 Gbps-capable transceivers for the GX version of this board. For the GT version,

Port A provides eight channels. The HSMC interface also supports a full SPI4.2

interface (17 LVDS channels), three input and output clocks, JTAG and SMB signals,

as well as power for compatible HSMC cards. The LVDS channels can be used for

CMOS signaling as well as LVDS.

1 The HSMC is an Altera-developed open specification, which allows you to expand

the functionality of the development board through the addition of daughtercards

(HSMCs).

f For more information about the HSMC specification such as signaling standards,

signal integrity, compatible connectors, and mechanical information, refer to the High

Speed Mezzanine Card (HSMC) Specification manual.

The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins,

and 13 ground pins. The ground pins are located between the two rows of signal and

power pins, acting both as a shield and a reference. The HSMC host connector is

based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board

connectors from Samtec. There are three banks in this connector. Bank 1 has every

third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have

all the pins populated as done in the QSH/QTH series.

Figure 2–10 shows the bank arrangement of signals with respect to the Samtec

connector's three banks.

The HSMC interface has programmable bi-directional I/O pins that can be used as

2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as

various differential I/O standards including, but not limited to, LVDS, mini-LVDS,

and RSDS with up to 17 full-duplex channels.

Figure 2–10. HSMC Signal and Bank Diagram

Bank 3

Power

D(79.40)

-or-

LVDS

CLKIN2, CLKOUT2

Bank 2

Power

D(39:0)

-or-

D[3:0] + LVDS

CLKIN1, CLKOUT1

Bank 1

8 TX Channels CDR

8 RX Channels CDR

JTAG

SMB

CLKIN0, CLKOUT0

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 89 90

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