Altera Arria V GX FPGA Development Board Manual do Utilizador descarregar pdf (Página 18)

2–8 Chapter 2: Board Components

Featured Device: Arria V GX FPGA

Arria V GX FPGA Development Board November 2013 Altera Corporation

Reference Manual

Table 2–4 lists the Arria V GX FPGA 2 pin count and usage by function on the

development board. Clocks are listed under special pins as it uses dedicated I/O pins.

Flash 1.8-V CMOS 49 —

PCI Express 2.5-V CMOS 10 1 reference clock

HSMC port A 2.5-V CMOS + LVDS 84 1 reference clock

Gigabit Ethernet 2.5-V CMOS + LVDS 16 —

On-Board USB-Blaster II 1.5-V/2.5-V CMOS 19 —

SFP+ 2.5-V CMOS 16 2 reference clocks

Chip-to-chip bridge 2.5-V 120 2 reference clocks

Buttons 2.5-V CMOS 3 —

Switches 2.5-V CMOS 4 —

LCD 2.5-V CMOS 11 —

LEDs 2.5-V CMOS 16 —

Clocks or Oscillators 1.8-V CMOS + LVDS 10 5 differential clocks, 1 single-ended

Total I/O Used:

625

Transceivers

SMA — 4 —

HSMC port A — 16 —

PCI Express — 32 —

Chip-to-chip bridge — 32 —

SFP+ — 4 —

Total Transceiver Used:

Table 2–4. Arria V GX FPGA 1 Pin Count and Usage (Part 2 of 2)

Function I/O Standard I/O Count Special Pins

Table 2–5. Arria V GX FPGA 2 Pin Count and Usage (Part 1 of 2)

Function I/O Standard I/O Count Special Pins

DDR3 ×64 device 1.5-V SSTL 156 1 differential ×9 differential DQS

HSMC port B 2.5-V CMOS + LVDS 84 1 reference clock

FMC 2.5-V 178 1 reference clock

SDI 2.5-V CMOS 8 1 reference clock

Chip-to-chip bridge 2.5-V 120 1 reference clock

Buttons 2.5-V CMOS 4 —

Switches 2.5-V CMOS 8 —

LEDs 2.5-V CMOS 16 —

Clocks or Oscillators 1.8-V CMOS + LVDS 10 5 differential clocks, 1 single-ended

Total I/O Used:

584

Transceivers

SMAs or Bull's Eye — 8 —

HSMC port B — 16 —

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 89 90

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