Altera Arria V GX FPGA Development Board Manual do Utilizador Página 12
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2–2 Chapter 2: Board Components
Board Overview
Arria V GX FPGA Development Board November 2013 Altera Corporation
Reference Manual
Board Overview
This section provides an overview of the Arria V GX FPGA development board,
including an annotated board image and component descriptions. Figure 2–1 shows
an overview of the available components.
Table 2–1 describes the components and lists their corresponding board references.
Figure 2–1. Overview of the Arria V GX FPGA Development Board Features
Arria V GX
FPGA
(U16)
Arria V GX FPGA (U13)
FMC Bank B Voltage Select (J11)
FMC VCCPD
B4 Select (J5)
FMC Bank B Power Source Select (J28)
MAX II CPLD
EPM2210 System
Controller (U2)
PCI
Express Edge
Connector
(J14)
JTAG Connector
(J1)
Embedded
USB-Blaster
Circuitry (J7)
Gigabit Ethernet
Port (J8)
SFP+ Port (J10)
SFP+ Port (J15)
[Available in
Arria V GT
Development
Kit only]
DC Input
Jack (J6)
Character
LCD (J29)
Board
Power Switch
(SW1)
ATX Power
Connector
(J4)
FMC
Connector
(J9)
CPU Reset
Push
Button (S4)
DDR3A
(U7, U11, U18,
U21, U28)
DDR3C
(U19, U22)
DDR3B (U6, U12)
Tx/Rx
Transceivers
(J19-J22)
Tx/Rx
Transceivers
(J12, J13,
J24, J25)
Fan Power
(J23)
Fan Power
(J14)
SDI Video
Port
(J26, J27)
Bullseye
SMA
Connector
(J16)
Clock Input
SMA
Connector
(J10, J11)
Configuration LEDs (D12-D17)
Configuration
Push Buttons
(S1-S3)
Flash
Memory (U4)
User LEDs (D18-D25)
User Push
Buttons
(S5-S7)
User LEDs (D26-D33)
User Push Buttons (S9-S11)
CPU Reset
Push Button (S8)
User DIP Switch (SW3)
User DIP
Switch (SW2)
HSMC
Port A (J2)
HSMC
Port B (J3)
Table 2–1. Arria V GX FPGA Development Board Components (Part 1 of 4)
Board Reference Type Description
Featured Devices
U13, U16 FPGA Two Arria V GX FPGA, 5AGXFB3HF40, 1517-pin FBGA.
U2 CPLD MAX II CPLD, EPM2210F324, 324-pin μBGA.
Configuration, Status, and Setup Elements
J1 JTAG connector
Disables the on-board USB-Blaster II (for use with external
USB-Blasters).
J7 On-Board USB-Blaster II Mini-USB 2.0 connector for programming and debugging the FPGA.
SW5 Board settings DIP switch
Controls the MAX
II CPLD EPM2210 System Controller functions such
as clock enable, SMA clock input control, and which image to load
from flash memory at power-up. This switch is located on the bottom
of the board.
SW6 JTAG chain DIP switch Enables and disables devices in the JTAG chain.
SW7 PCI Express DIP switch
Controls the PCI Express lane width by connecting
prsnt
pins
together on the PCI Express edge connector. This switch is located on
the bottom of the board.
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Dual FPGA 7
- 1–4 Chapter 1: Overview 8
- 1–6 Chapter 1: Overview 10
- Handling the Board 10
- 2. Board Components 11
- Board Overview 12
- I/O Resources 17
- II CPLD EPM2210 System 20
- II device (U2) 20
- Table 2–7 lists the MAX 24
- Configuration 25
- Figure 2–4. JTAG Chain 26
- Figure 2–5. PFL Configuration 28
- Status Elements 29
- Setup Elements 31
- JTAG Settings DIP Switch 32
- CPU Reset Push Button 33
- MAX II Reset Push Button 33
- Clock Circuitry 34
- FPGA development board 35
- Off-Board Clock Input/Output 37
- General User Input/Output 39
- User-Defined DIP Switches 40
- User-Defined LEDs 41
- HSMC User-Defined LEDs 42
- SDI Video Output/Input 44
- Components and Interfaces 47
- 10/100/1000 Ethernet 50
- SFP+ Module 59
- FMC Connector 60
- Bull's Eye Connector 67
- DDR3A for FPGA 1 68
- I/O setting and direction 69
- DDR3B/C for FPGA 2 73
- Power Supply 83
- Power Measurement 85
- Notes to Table 2–64: 87
- Info–2 Additional Information 90
- Typographic Conventions 90
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