Altera Arria V GX FPGA Development Board Manual do Utilizador descarregar pdf (Página 23)

Chapter 2: Board Components 2–13

MAX II CPLD EPM2210 System Controller

November 2013 Altera Corporation Arria V GX FPGA Development Board

Reference Manual

FPGA2_MSEL3

T7 2.5-V FPGA 2 mode select 3

FPGA2_MSEL4

U6 2.5-V FPGA 2 mode select 4

FPGA2_NCONFIG

M2 2.5-V FPGA 2 configuration active

FPGA2_NSTATUS

M6 2.5-V FPGA 2 configuration ready

FPGA2_PR_DONE

B16 2.5-V FPGA 2 partial reconfiguration done

FPGA2_PR_ERROR

D14 2.5-V FPGA 2 partial reconfiguration error

FPGA2_PR_READY

A17 2.5-V FPGA 2 partial reconfiguration ready

FPGA2_PR_REQUEST

E13 2.5-V FPGA 2 partial reconfiguration request

FPGA_DCLK

N2 2.5-V FPGA configuration clock

HSMA_PRSNTN

A14 2.5-V HSMC port A present

HSMB_PRSNTN

E11 2.5-V HSMC port B present

INIT_DONE1

T6 2.5-V FPGA initialization done

INIT_DONE2

V4 2.5-V FPGA initialization done

JTAG_EPM2210_TDI

M7 2.5-V MAX II CPLD on-board JTAG chain data in

JTAG_BLASTER_TDI

N6 2.5-V MAX II CPLD on-board JTAG chain data out

JTAG_TCK

R4 2.5-V JTAG chain clock

JTAG_TMS

P5 2.5-V JTAG mode select

M570_CLOCK

A10 1.8-V

25-MHz clock to the on-board USB-Blaster II for sending

FACTORY command

M570_PCIE_JTAG_EN

D9 1.8-V

Low signal to disable the on-board USB-Blaster II when the

PCI Express acts as a master to the JTAG chain.

MAX_BEN0

B11 2.5-V FM bus MAX II byte enable 0

MAX_BEN1

C10 2.5-V FM bus MAX II byte enable 1

MAX_BEN2

A11 2.5-V FM bus MAX II byte enable 2

MAX_BEN3

C9 2.5-V FM bus MAX II byte enable 3

MAX_CLK

J18 1.8-V FM bus MAX II clock

MAX_CSN

J17 1.8-V FM bus MAX II chip select

MAX_OEN

J15 1.8-V FM bus MAX II output enable

MAX_WEN

J14 1.8-V FM bus MAX II write enable

MAX_CONF_DONE1

B3 2.5-V FPGA configuration done LED

MAX_CTL0

E10 2.5-V FPGA 1 to MAX II option

MAX_CTL1

A12 2.5-V FPGA 1 to MAX II option

MAX_CTL2

D10 2.5-V FPGA 1 to MAX II option

MAX_ERROR1

C7 2.5-V FPGA 1 configuration error LED

MAX_LOAD1

B6 2.5-V FPGA 1 configuration active LED

MAX_RESETN

E18 1.8-V MAX II reset push button

OVERTEMP1

B14 2.5-V FPGA 1 fan RPM control

OVERTEMP2

C12 2.5-V FPGA 2 fan RPM control

PGM1_CONFIG

B4 2.5-V Load the flash memory image identified by the PGM LEDs

Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 5)

Schematic Signal Name

MAX II CPLD

Pin Number

I/O Standard Description

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 89 90

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