Altera ALTDQ_DQS2 Manual do Utilizador descarregar pdf (Página 68)

18.675 us, the enable_driver signal is asserted to specify that the internal calibration is completed. The

DQS driver, which acts as the host controller, performs a read/write operation.

Note: For RTL related to dynamic configuration operations in this design example, refer to

config_controller.sv file.

To help you achieve static timing closure, the dynamic configuration feature allows you to override the

static values at runtime with a scan chain. Each l/O and the DQS logic contains its own scan chain block

(shift registers). This section shows you how to serially scan configuration bits into each scan chain block,

between 100 ns and 18.675 us.

The following figure shows the waveform for the dynamic configuration simulation generated after

executing topwave.do (located in the simulation/modelsim folder), in between the high pulses of

beginscan and scandone. There is a pulse between 18.035 us and 18.075 us on the config_data_in

signal. This is because the dqsinputphasesetting of the DQS configuration is set to 2'b01 in the

testbench.

Note: For the results of this settings, refer to DQS Delay Chain on page 70.

Figure 32: Dynamic Configuration Waveform

Because the enable_driver signal is asserted at 18.675 us, the DQS driver performs the following

operations:

• DQS Write Operation on page 68

• Side Read Operation on page 69

• Side Write Operation on page 69

• DQS Read Operation on page 70

Note:

The driver_clk clock is running at the same rate as the core).

Related Information

• Dynamic Reconfiguration for ALTDQ_DQS2 on page 38

DQS Write Operation

The driver asserting the dqs_enable signal at 18.803 µs begins the write operation. The dqs_write signal

is asserted at 18.811 µs. The write_oe_in signal of the ALTDQ_DQS2 IP core is set to high and is ready

to send data to the DQS agent. Data are written to the dqs_writedata of the DQS driver and then

reflected in the dq signal of the ALTDQ_DQS2 IP core. The data written out from the DQS driver are

stored in check/i/o. The dqs_write signal deasserts at 18.851 µs. The dqs_enable deasserts at 18.859 µs.

Outgoing data from the ALTDQ_DQS2 (dq) is center aligned to the write clock (dqs_ios_to_agent).

The following figure shows the DQS write operation waveform.

DQS Write Operation

UG-01089

2014.12.17

Altera Corporation

ALTDQ_DQS2 IP Core User Guide

Send Feedback

1 2 ... 63 64 65 66 67 68 69 70 71 72 73 ... 99 100

Sem comentários

Altera ALTDQ_DQS2 Manual do Utilizador Página 68