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Table 14: DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices

Legend in I/O Configu‐

ration Block Bit

Sequence for Arria V

GZ and Stratix V

Devices on page 40

Bit Bit Name Description

E 5..0 dqsbusoutdelaysetting Connects to the delayctrlin port

of the first D4 delay chain.

Controls the first D4 delay chain

in DQS delay chain path (after

the DQS delay chain). This is the

delay tuning of the DQS signal

feeding into the DQS bus.

For delay values, refer to the

“Programmable IOE Delay”

section in the Stratix V Device

Datasheet.

F 11..6 dqsbusoutdelaysetting2 Connects to the delayctrlin port

of the second D4 delay chain.

Controls the second D4 delay

chain in DQS delay chain path

(after the first D4 delay chain).

This is the delay tuning of the

DQS signal feeding into the DQS

bus.

For delay values, refer to the

“Programmable IOE Delay”

section in the Stratix V Device

Datasheet.

G 17..12 octdelaysetting1 Connects to the delayctrlin port

of the D5 OCT delay chain.

Controls the dynamic OCT

output register-to-I/O buffer

delay chain (D5).

For delay values, refer to the

“Programmable IOE Delay”

section in the Stratix V Device

Datasheet.

UG-01089

2014.12.17

DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices

ALTDQ_DQS2 IP Core User Guide

Altera Corporation

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