Altera ALTDQ_DQS2 Manual do Utilizador descarregar pdf (Página 41)

100

Legend

Figure

Bit

Bit Name Description

B 11..6 padtoinputregisterrisefalldelaysetting Connects to the delayctrlin port of

the second D1 delay chain to control the

second pad-to-input register delay chain

(D1).

For delay values, refer to the “Program‐

mable IOE Delay” section in the Stratix

V Device Datasheet.

C 17..12 outputdelaysetting1 Connects to the delayctrlin port of

the D5 delay chain to control the output

in the output path and output enable

paths.

This delay is for write calibration for

DDR application.

For delay values, refer to the “Program‐

mable IOE Delay” section in the Stratix

V Device Datasheet.

D 23..18 outputdelaysetting2 Connects to the delayctrlin port of

the second D5 delay chain to control the

output register-to-I/O buffer delay chain

(second D5) in the output path and

output enable paths.

This delay is for write calibration for

DDR application.

For delay values, refer to the “Program‐

mable IOE Delay” section in the Stratix

V Device Datasheet.

— 39..24 inputclkndelaysetting

inputclkdelaysetting

dutycycledelaymode

dutycycledelaysetting

Unconfigurable bits.

Always set bits to its default value.

UG-01089

2014.12.17

I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices

ALTDQ_DQS2 IP Core User Guide

Altera Corporation

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