Altera ALTDQ_DQS2 Manual do Utilizador descarregar pdf (Página 57)

100

Legend in Figure 19 Bit Bit Name Description

H 9..5 dqsenablegatingdelaysetting Connects to the delayctrlin port

of the postamble T11 delay

chain (gated). Aligns the

postamble signal in terms of

DQS signal by selecting

different delays.

I 10 enadqsenablephasetransferreg Connects to the enaphasetrans‐

ferreg port of the DQS Enable

Control block to allow an

additional negative edge-

triggered register to be added to

the DQS enable control path to

satisfy the setup or hold time

requirement for the phase

transfer.

J 15..11 octdelaysetting Connects to the delayctrlin port

of the D5 delay chain.

Controls the dynamic OCT

output register-to-I/O buffer

delay chain (D5).

For delay values, refer to the

“Programmable IOE Delay”

sections in the Arria V Device

Datasheet and the Cyclone V

Device Datasheet, respectively.

K 16 dqshalfratebypass Sets the multiplexers in the DQS

enable logic, OCT logic, and

FIFO control logic to

dynamically switch from half-

rate to full-rate configuration.

L 21..17 dqsbusoutdelaysetting Connects to the delayctrlin port

of the read DQS D4 delay chain.

Controls the delay tuning of the

DQS signal feeding into the

DQS bus.

UG-01089

2014.12.17

DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices

ALTDQ_DQS2 IP Core User Guide

Altera Corporation

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