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19–2 Chapter 19: Migrating from Stratix IV to Stratix V Devices

Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Differences in Dynamic Reconfiguration for Stratix IV and Stratix V

Transceivers

Dynamic reconfiguration interface is completely new in Stratix V devices. You cannot

automatically migrate a dynamic reconfiguration solution from Stratix IV to Stratix V

devices.

Stratix V devices that include transceivers must use the Altera Transceiver

Reconfiguration Controller that contains the offset cancellation logic to compensate

for variations due to PVT. Initially, each transceiver channel and each TX PLL has its

own parallel, dynamic reconfiguration bus, named

reconfig_from_xcvr[45:0]

and

reconfig_to_xcvr[69:0]

. The reconfiguration bus includes Avalon-MM signals to

read and write registers and memory and test bus signals. When you instantiate a

transceiver PHY in a Stratix V device, the transceiver PHY IP core provides

informational messages specifying the number of required reconfiguration interfaces

in the message pane as Example 19–1 illustrates.

Although you must initially create a separate reconfiguration interface for each

channel and TX PLL in your design, when the Quartus II software compiles your

design, it reduces the number of reconfiguration interfaces by merging

reconfigurations interfaces. The synthesized design typically includes a

reconfiguration interface for three channels. Allowing the Quartus II software to

merge reconfiguration interfaces gives the Fitter more flexibility in placing transceiver

channels.

Stratix IV devices that include transceivers must use the ALTGX_RECONFIG IP Core

to implement dynamic reconfiguration. The ALTGX_RECONFIG IP Core always

includes the following two serial buses:

■

reconfig_from[<n>16:0]

— this bus connects to all the channels in a single quad.

<n> is the number of quads connected to the ALTGX_RECONFIG IP Core.

■

reconfig_togxb[3:0]

—this single bus connects to all transceiver channels.

If you select additional functionality in the MegaWizard Plug-In Manager for the

ALTGX_RECONFIG IP Core, the IP core adds signals to support that functionality.

For more information about the ALTGX_RECONFIG IP Core, refer to

ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices in volume 3 of the

Stratix IV Device Handbook.

Example 19–1. Informational Messages for the Transceiver Reconfiguration Interface

PHY IP will require 5 reconfiguration interfaces for connection to the external

reconfiguration controller.

Reconfiguration interface offsets 0-3 are connected to the transceiver channels.

Reconfiguration interface offset 4 is connected to the transmit PLL.

1 2 ... 451 452 453 454 455 456 457 458 459 460 461 ... 483 484

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