Altera UG-01080 Guia do Utilizador descarregar pdf (Página 162)

100

101

8–10 Chapter 8: PHY IP Core for PCI Express (PIPE)

Clocks

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Figure 8–4 illustrates the

pipe_pclk

switching from Gen1 to Gen2 and then to Gen3.

Clocks

Table 8–6 describes the clock ports.

rxstatus<n>[2:0]

Output

This signal encodes receive status and error codes for the receive data

stream and receiver detection.The following encodings are defined:

■ 3’b000–receive data OK

■ 3’b001–1 SKP added

■ 3’b010–1 SKP removed

■ 3’b011–Receiver detected

■ 3’b100–Both 8B/10B or 128b/130b decode error and (optionally) RX

disparity error

■ 3’b101–Elastic buffer overflow

■ 3’b110–Elastic buffer underflow

■ 3’b111–Receive disparity error, not used if disparity error is reported

using 3’b100.

pipe_phystatus

Output This signal is used to communicate completion of several PHY requests.

Table 8–5. Avalon-ST RX Inputs (Part 2 of 2)

Signal Name Dir Description

Figure 8–4. Rate Switch from Gen1 to Gen2 Timing Diagram

Note to Figure8–4:

(1) Time T1 is pending characterization.

(2) <n> is the number of lanes.

pipe_pclk

pipe_rate[1:0]

0 1 0 2

T1 T1

62.5 MHz (Gen1)

250 MHz (Gen3)

125 MHz (Gen2)

pipe_phystatus[<n>-1:0]

Table 8–6. Clock Ports

Signal Name Direction Description

pll_ref_clk

Input

This is the 100 MHz input reference clock source for the PHY TX and

RX PLL. You can optionally provide a 125 MHz input reference clock

by setting the PLL reference clock frequency parameter to 125 MHz

as described in PHY IP Core for PCI Express General Options.

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