Altera UG-01080 Guia do Utilizador Página 26

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3–4 Chapter 3: 10GBASE-R PHY IP Core
Altera Transceiver PHY IP Core November 2012 Altera Corporation
User Guide
Figure 3–5 illustrates the 10GBASE-R PHY for Stratix V devices.
Table 31 lists the latency through the PCS and PMA for Arria V GT devices with a
66-bit PMA. The FPGA fabric to PCS interface is 66 bits wide. The frequency of the
parallel clock is 156.25 MHz which is line rate (10.3125 Gbps)/interface width (66).
Table 32 lists the latency through the PCS and PMA for Stratix V devices with a
40-bit PMA. The FPGA fabric to PCS interface is 66 bits wide. The frequency of the
parallel clock is 156.25 MHz which is line rate (10.3125 Gbps)/interface width (66).
Figure 3–5. 10GBASE-R PHY IP Core In Stratix V Devices
Data
Wiring
PLD-PCS & Duplex PCS
PCS-PMA
PCS
TX PMA
PMA
RX PMA & CDR
Generic
PLL
Reset
Controller
PMA + Reset Control & Status
(Memory Map)
Tx Serial
Rx Serial
S
Control & Status
(Optional or by
I/F Specification)
Avalon-ST
Streaming
Data
Tx Data
Rx Data
Transceiver Protocol
Stratix V Transceiver Protocol
To/From
XCVR
Avalon-MM Slave
Avalon-MM Master
S
M
Avalon-MM
Management
Interface
to Embedded
Controller
Transceiver
Reconfiguration
Controller
S
Table 3–1. Latency for TX and RX PCS and PMA Arria V Devices
PCS (Parallel Clock Cycles) PMA (UI)
TX 28 131
RX 33 99
Table 3–2. Latency for TX and RX PCS and PMA Stratix V Devices
PCS (Parallel Clock Cycles)
PMA (UI)
Minimum Maximum
TX 8 12 124
RX 15 34 43
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