Altera UG-01080 Guia do Utilizador descarregar pdf (Página 223)

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Chapter 11: Deterministic Latency PHY IP Core 11–9

General Options Parameters

November 2012 Altera Corporation Altera Transceiver PHY IP Core

User Guide

Table 11–7 lists the available channel widths available at selected frequencies. The

channel width options are restricted by the following maximum FPGA-PCS fabric

interface frequencies:

■ Arria V devices—153.6 MHz

■ Cyclone V devices—153.6 MHz

■ Stratix V devices—221 MHz

Input clock frequency

Data rate/20

Data rate/10

Data rate/8

Data rate/5

Data rate/4

Data rate/2.5

Data rate/2

Data rate/1.25

Data rate/1

This is the reference clock for the PHY PLL. The available options are

based on the Base data rate specified.

Enable tx_clkout feedback path

for TX PLL

On/Off

When On, the

core uses TX PLL feedback to align the TX core clock

with the source to the TX PLL which is the RX recovered clock. This

configuration is shown in Using TX PLL Feedback to Align the TX

Core Clock with the RX Core Clock

Table 11–6. General Options (Part 2 of 2)

Name Value Description

Table 11–7. Sample Channel WIdth Options for Supported Serial Data Rates

Serial Data Rate (Mbps)

Channel Width (FPGA-PCS Fabric)

Single-Width Double-Width

8-Bit 16-Bit 16-Bit 32-Bit

614.4 vv——

1228.8 vvvv

2457.6 — vvv

3072 — v v v

4915.2 — — — v

6144 — — — v

1 2 ... 218 219 220 221 222 223 224 225 226 227 228 ... 483 484

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