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10–6 Chapter 10: Low Latency PHY IP Core

Additional Options Parameters

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Table 10–5 describes the options available on the Additional Options tab.

Table 10–5. Additional Options (Part 1 of 2)

Name Value Description

Enable tx_coreclkin On/Off

When you turn this option on,

tx_coreclkin

connects to the

write clock of the TX phase compensation FIFO and you can clock

the parallel TX data generated in the FPGA fabric using this port.

This port allows you to clock the write side of the TX phase

compensation FIFO with a user-provided clock, either the FPGA

fabric clock, the FPGA fabric-TX interface clock, or the input

reference clock. You must turn this option On when the FPGA

fabric transceiver interface width:PCS-PMA Interface width is

50:40 or when you specify the 10G datapath with a fabric

transceiver interface width:PCS-PMA Interface width of 64:32.

For the GT datapath, if you are using different reference clock pins

for the TX and RX channels, you must instantiate two separate Low

Latency PHY IP Core instances for TX and RX channels. The

reference clock pins for each channel must reside in the same

transceiver bank.

For more information refer to the “FPGA Fabric-Transceiver

Interface Clocking” section in the Stratix V Transceiver Clocking

chapter.

Enable rx_coreclkin On/Off

When you turn this option on,

rx_coreclkin

connects to the read

clock of the RX phase compensation FIFO and you can clock the

parallel RX output data using

rx_coreclk

. This port allows you to

clock the read side of the RX phase compensation FIFO with a

user-provided clock, either the FPGA fabric clock, the FPGA fabric

RX interface clock, or the input reference clock. rx_coreclkin is not

available for the GT datapath.

You must turn this option On when the FPGA fabric transceiver

interface width:PCS-PMA Interface width is 50:40 or when you

specify the 10G datapath with a fabric transceiver interface

width:PCS-PMA Interface width of 64:32.

For more information refer to the “FPGA Fabric-Transceiver

Interface Clocking” section in the Stratix V Transceiver Clocking

chapter.

Enable TX bitslip On/Off

The bit slip feature allows you to slip the transmitter side bits

before they are sent to the gearbox. The maximum number of bits

slipped is equal to the ((FPGA fabric-to-transceiver interface width)

– 1). For example, if the FPGA fabric-to-transceiver interface width

is 64 bits, the bit slip logic can slip a maximum of 63 bits. Each

channel has 5 bits to determine the number of bits to slip. The

value specified on the TX bitslip bus indicates the number of bit

slips. Effectively, each value shifts the word boundary by one bit.

For example, a TX bitslip value of 1 on a 64bit FPGA interface width

shifts the word boundary by 1 bit. That is, bit[63] from the first

word and bit[62:0] are concatenated to form a 64 bit word

(bit[62:0] from the second word, bit[63] from the first word LSB).

This option is only available for the Standard and 10G datapaths.

Enable RX bitslip On/Off

When enabled, the word-aligner operates in bitslip mode. This

option is available for Stratix V and Arria V GZ devices using the

10G datapath.

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