Altera DDR SDRAM High-Performance Controllers and ALTMEMP Manual do Utilizador Página 9
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Chapter 1: About This IP 1–3
Features
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Table 1–2 shows the level of support offered by the DDR and DDR2 SDRAM
Controllers with ALTMEMPHY IP to each of the Altera device families.
Features
The ALTMEMPHY megafunction offers the following features:
■ Simple setup.
■ Support for the Altera PHY Interface (AFI) for DDR and DDR2 SDRAM on all
supported devices.
■ Automated initial calibration eliminating complicated read data timing
calculations.
■ Voltage and temperature (VT) tracking that guarantees maximum stable
performance for DDR and DDR2 SDRAM interfaces.
■ Self-contained datapath that makes connection to an Altera controller or a
third-party controller independent of the critical timing paths.
■ Full-rate and half-rate DDR and DDR2 SDRAM interfaces.
■ Easy-to-use parameter editor.
In addition, Table 1–3 shows the features provided by the DDR and DDR2 SDRAM
HPC II.
Table 1–2. Device Family Support
Device Family Support
Arria
®
GX Final
Arria II GX Final
Cyclone
®
III Final
Cyclone III LS Final
Cyclone IV E Final
Cyclone IV GX Final
HardCopy II HardCopy Companion
Stratix
®
II Final
Stratix II GX Final
Other device families No support
Table 1–3. DDR and DDR2 SDRAM HPC and HPC II Features (Part 1 of 2)
Features HPC II
Half-rate controller v
Support for AFI ALTMEMPHY v
Support for Avalon
®
Memory Mapped (MM) local interface v
Configurable command look-ahead bank management with in-order reads
and writes
v
Additive latency v (1)
Support for arbitrary Avalon burst length v
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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