Altera DDR SDRAM High-Performance Controllers and ALTMEMP Manual do Utilizador Página 11
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Chapter 1: About This IP 1–5
Resource Utilization
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Resource Utilization
Table 1–4 through Table 1–6 show typical resource utilization data for the DDR2
high-performance controller and controller plus PHY, for half-rate and full-rate
configurations.
Table 1–4. DDR2 Resource Utilization in Arria II GX Devices
Protocol
Memory
Width
(Bits)
Combinational
ALUTS
Logic
Registers
Mem
ALUTs
M9K
Blocks
M144K
Blocks
Memory
(Bits)
Controller
DDR2
(Half rate)
8 1,971 1,547 10 2 0 4,352
16 1,973 1,547 10 4 0 8,704
64 2,028 1,563 18 15 0 34,560
72 2,044 1,547 10 17 0 39,168
DDR2
(Full rate)
8 2,007 1,565 10 2 0 2,176
16 2,013 1,565 10 2 0 4,352
64 2,022 1,565 10 8 0 17,408
72 2,025 1,565 10 9 0 19,584
Controller+PHY
DDR2
(Half rate)
8 3,481 2,722 12 4 0 4,672
16 3,545 2,862 12 7 0 9,280
64 3,891 3,704 20 24 0 36,672
72 3,984 3,827 12 26 0 41,536
DDR2
(Full rate)
8 3,337 2,568 29 2 0 2,176
16 3,356 2,558 11 4 0 4,928
64 3,423 2,836 31 12 0 19,200
72 3,445 2,827 11 14 0 21,952
Table 1–5. DDR2 Resource Utilization in Cyclone III Devices (Part 1 of 2)
Protocol
Memory
Width (Bits)
Logic
Registers
Logic Cells M9K Blocks
Memory
(Bits)
Controller
DDR2
(Half rate)
8 1,513 3,015 4 4,464
16 1,513 3,034 6 8,816
64 1,513 3,082 18 34,928
72 1,513 3,076 19 39,280
DDR2
(Full rate)
8 1,531 3,059 4 2,288
16 1,531 3,108 4 4,464
64 1,531 3,134 10 17,520
72 1,531 3,119 11 19,696
- ALTMEMPHY IP User Guide 1
- Contents 3
- Chapter 7. Latency 5
- Chapter 8. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- Features 9
- Unsupported Features 10
- MegaCore Verification 10
- Resource Utilization 11
- System Requirements 12
- Installation and Licensing 13
- 1–8 Chapter 1: About This IP 14
- 2. Getting Started 15
- SOPC Builder Flow 16
- Qsys Flow 18
- Completing the Qsys System 19
- Specifying Parameters 20
- HardCopy Guidelines 21
- Generated Files 22
- 3. Parameter Settings 27
- Memory Settings 28
- ALTMEMPHY Parameter Settings 29
- Note to Table 3–3: 32
- Note to Table 3–5: 34
- PHY Settings 36
- Board Settings 38
- ■ Memory Settings 39
- ■ PHY Settings 39
- ■ Board Settings 39
- ■ Controller Settings 39
- Controller Settings 40
- 4. Compiling and Simulating 43
- Compiling the Design 44
- Simulating the Design 46
- Block Description 48
- Calibration 49
- Address and Command Datapath 49
- ), or the inverted 50
- Clock and Reset Management 51
- Notes to Table 5–4: 54
- Note to Table 5–2: 57
- Cyclone III Devices 59
- Read Datapath 66
- Note to Figure 5–6: 68
- Note to Figure 5–8: 70
- Devices 71
- GX Devices 72
- ALTMEMPHY Signals 73
- Notes to Table 5–5: 74
- Note to Table 5–5: 77
- Notes to Table 5–7: 79
- PHY-to-Controller Interfaces 80
- Altera Device 81
- -- a --b 82
- Figure 5–15. Full-Rate Reads 83
- Figure 5–16. Half-Rate Reads 83
- Notes to Figure 5–17: 85
- Notes to Figure 5–18: 86
- Notes to Figure 5–19: 87
- Notes to Figure 5–20: 88
- Preliminary Steps 89
- Design Considerations 89
- Clocks and Resets 89
- Using a Custom Controller 90
- Partial Write Operations 92
- 6. Functional Description— 95
- Avalon-ST Input Interface 96
- Command Generator 96
- Timing Bank Pool 96
- Arbitration Rules 97
- CSR Interface 98
- Data Reordering 98
- Pre-emptive Bank Management 98
- Quasi-1T and Quasi-2T 98
- User Autoprecharge Commands 98
- User-Controlled Self-Refresh 99
- DDR2 SDRAM 100
- Partial Writes 101
- Partial Bursts 102
- External Interfaces 103
- Memory Side-Band Signals 104
- Top-Level Signals Description 105
- ■ Full rate controllers 107
- ■ Half rate controllers 107
- Sequence of Operations 111
- Read Command 112
- Read-Modify-Write Command 112
- Example Top-Level File 113
- Example Driver 114
- Register Maps 116
- Controller Register Map 118
- 7. Latency 123
- 7–2 Chapter 7: Latency 124
- Note to Table 7–2: 125
- SDRAM values 126
- Handbook 127
- 7–6 Chapter 7: Latency 128
- 8. Timing Diagrams 129
- Half-Rate Read 130
- Half-Rate Write 132
- Full-Rate Read 134
- Full-Rate Write 136
- Additional Information 139
- Typographic Conventions 140
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