manuais Altera DDR SDRAM High-Performance Controllers and ALTMEMP

Manuais de instruções e guias do utilizador para Instrumentos de medida Altera DDR SDRAM High-Performance Controllers and ALTMEMP.
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Altera DDR SDRAM High-Performance Controllers and ALTMEMP Manual do Utilizador (140 páginas)

Marca: Altera | Categoria: Instrumentos de medida | Tamanho: 2.82 MB |

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ALTMEMPHY IP User Guide

Contents

Chapter 7. Latency

Chapter 8. Timing Diagrams

1. About This IP

Release Information

Device Family Support

Features

Unsupported Features

MegaCore Verification

Resource Utilization

System Requirements

Installation and Licensing

1–8 Chapter 1: About This IP

2. Getting Started

SOPC Builder Flow

Qsys Flow

Completing the Qsys System

Specifying Parameters

HardCopy Guidelines

Generated Files

3. Parameter Settings

Memory Settings

ALTMEMPHY Parameter Settings

Note to Table 3–3:

Note to Table 3–5:

PHY Settings

Board Settings

■ Memory Settings

■ PHY Settings

■ Board Settings

■ Controller Settings

Controller Settings

4. Compiling and Simulating

Compiling the Design

Simulating the Design

Block Description

Calibration

Address and Command Datapath

), or the inverted

Clock and Reset Management

Notes to Table 5–4:

Note to Table 5–2:

Cyclone III Devices

Read Datapath

Note to Figure 5–6:

Note to Figure 5–8:

Devices

GX Devices

ALTMEMPHY Signals

Notes to Table 5–5:

Note to Table 5–5:

Notes to Table 5–7:

PHY-to-Controller Interfaces

Altera Device

-- a --b

Figure 5–15. Full-Rate Reads

Figure 5–16. Half-Rate Reads

Notes to Figure 5–17:

Notes to Figure 5–18:

Notes to Figure 5–19:

Notes to Figure 5–20:

Preliminary Steps

Design Considerations

Clocks and Resets

Using a Custom Controller

Partial Write Operations

6. Functional Description—

Avalon-ST Input Interface

Command Generator

Timing Bank Pool

Arbitration Rules

CSR Interface

Data Reordering

Pre-emptive Bank Management

Quasi-1T and Quasi-2T

User Autoprecharge Commands

User-Controlled Self-Refresh

DDR2 SDRAM

100

Partial Writes

101

Partial Bursts

102

External Interfaces

103

Memory Side-Band Signals

104

Top-Level Signals Description

105

■ Full rate controllers

107

■ Half rate controllers

107

Sequence of Operations

111

Read Command

112

Read-Modify-Write Command

112

Example Top-Level File

113

Example Driver

114

116

Controller Register Map

118

7. Latency

123

7–2 Chapter 7: Latency

124

Note to Table 7–2:

125

SDRAM values

126

Handbook

127

7–6 Chapter 7: Latency

128

8. Timing Diagrams

129

Half-Rate Read

130

Half-Rate Write

132

Full-Rate Read

134

Full-Rate Write

136

Additional Information

139

Typographic Conventions

140

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manuais Altera DDR SDRAM High-Performance Controllers and ALTMEMP

Altera DDR SDRAM High-Performance Controllers and ALTMEMP Manual do Utilizador (140 páginas)

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