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Figure 5: Output Path

This figure shows the output path for the Altera PHYLite for Parallel Interfaces IP core.

Write FIFO

data_io

data_out

oe_out

oct_out

Interpolator

interpolator_clk

data_from_core

oe_from_core

phy_clk

VCO clock

output_strobe_in

output_strobe_en

strobe_out

strobe_io

Table 2: Blocks in Output Path

This table lists the blocks in the output path.

Block Description

FIFO Serializes the output data from the core with a serialization factor of up to 8

(in DDR quarter-rate).

Interpolator Works with the FIFO block to generate the desired output delay. You can

dynamically configure the delay through the Avalon interface. For more

information, refer to Dynamic Reconfiguration on page 20.

Output Path

ug_altera_phylite

2015.01.16

Altera Corporation

Altera PHYLite for Parallel Interfaces IP Core User Guide

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