Altera PHYLite Manual do Utilizador descarregar pdf (Página 5)

Interface

Figure 4: Top-Level Interface

This figure shows the top-level diagram of the Altera PHYLite for Parallel Interfaces IP core interface.

PLL

I/O Lane

Tile Control

I/O Lane

VCO/Interpolator

phy_clk

phy_clk_phs

core_clk_out

data_in/out/io

Data to/from Core

Group

ref_clk

Reference Clock

Core Clock

PHY Clock

ExternalClock

Legend

The Altera PHYLite for Parallel Interfaces IP core consists of the following interfaces:

• Clocks and Reset

• Core Data and Control (broken down into input and output paths)

• I/O (broken down into input and output paths)

• Avalon Configuration Bus

Related Information

• Output Path on page 5

For more information about the output path

• Input Path on page 8

For more information about the input path

• Signals on page 37

For more information about core data, control, and I/O interfaces signals

Output Path

The output path consists of a FIFO and an interpolator.

ug_altera_phylite

2015.01.16

Interface

Altera PHYLite for Parallel Interfaces IP Core User Guide

Altera Corporation

Send Feedback

1 2 3 4 5 6 7 8 9 10 ... 60 61

Sem comentários

Altera PHYLite Manual do Utilizador Página 5