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Signal Name Direction Width Description
avl_readdata_valid Output 1 Indicates that read data has returned.
avl_waitrequest Output 1 Stalls upstream logic when it is asserted.
Table 22: Avalon-MM Slave Interface Signals
Signal Name Direction Width Description
avl_out_clk Output 1 Connect this signal to the input Avalon interface of
another Altera PHYLite for Parallel Interfaces IP core or
the Arria 10 External Memory Interfaces IP.
avl_out_reset_n Output 1 Connect this signal to the input Avalon interface of
another Altera PHYLite for Parallel Interfaces IP core or
the Arria 10 External Memory Interfaces IP.
avl_out_read Output 1 Indicates read transaction.
avl_out_write Output 1 Indicates write transaction.
avl_out_byteenable Output 4 Controls which bytes should be written on avl_out_
writedata.
avl_out_writedata Output 32 The data packet associated with the write transaction.
avl_out_address Output 28 Avalon address (in byte granularity). Value is identical to
avl_address but with zeroes padded on the LSBs.
avl_out_readdata Input 32 The data packet associated with avl_out_readdata_
valid.
avl_out_readdata_
valid
Input 1 Indicates that read data has returned.
avl_out_waitrequest Input 1 Stalls upstream logic when it is asserted.
Related Information
Dynamic Reconfiguration on page 20
For more information about connecting these signals
Example Design
The Altera PHYLite for Parallel Interfaces IP core is able to generate an example design that matches the
same configuration chosen for the IP. The example design is a simple design that does not target any
specific application; however you can use the example design as a reference on how to instantiate the IP
core and what behavior to expect in a simulation.
Note:
The .qsys files are for internal use during example design generation only. You should not edit the
files.
42
Example Design
ug_altera_phylite
2015.01.16
Altera Corporation
Altera PHYLite for Parallel Interfaces IP Core User Guide
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- Device Family Support 1
- Features 1
- Overview 2
- Related Information 3
- Clock Frequency Relationships 4
- Interface 5
- Output Path 5
- Block Description 6
- Output Path Data Alignment 7
- Input Path 8
- Path Description 9
- Legend in Figure 9 Operation 9
- Input Path Data Alignment 10
- I/O Standards 11
- 2015.01.16 12
- Input Buffer 13
- VREF Calibration Block 13
- Resistor 13
- Altera Corporation 14
- Send Feedback 14
- Calibrated VREF Settings 14
- Placement Restrictions 15
- Reference Clock 16
- Dynamic Reconfiguration 16
- Timing Components 17
- Timing Constraints and Files 17
- Timing Analysis 18
- Timing Closure Guidelines 19
- Addressing 21
- Feature Avalon Address R/ 22
- Address CSR R Control Value 22
- Field Range 22
- Address Look-Up 25
- Component Description 26
- 32-bits (4 Byte Addresses) 27
- Parameter Table Example 29
- Calibration Guidelines 31
- Parameter Settings 31
- GUI Name Values Description 32
- Read Latencies 37
- Output Path Signals 38
- Input Path Signals 40
- Example Design 42
- Generating Example Design 43
- Common Parameters 46
- Parameter Description 48
- Section Parameter Description 50
- Signal Type Description 52
- Interfaces IP Core 58
- Signal Description 59
- Document Revision History 60
- Date Version Changes 61
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