Altera Low Latency Ethernet 10G MAC Manual do Utilizador Página 71
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Table 4-10: TX Timestamp Registers
Word
Offset
Register Name Description Access HW Reset
Value
0x0100 tx_period_10G
Specifies the clock period for the
timestamp adjustment on the TX datapath
for 10G operations. The MAC IP core
multiplies the value of this register by the
number of stages separating the actual
timestamp and XGMII bus.
• Bits 15:0—period in fractional
nanoseconds.
• Bits 19:16—period in nanoseconds.
• Bits 31:20—reserved. Set these bits to 0.
The default value is 3.2 ns for 312.5 MHz
clock. Configure this register before you
enable the MAC IP core for operations.
RW
0x33333
0x0102 tx_fns_adjustment_10G Static timing adjustment in fractional
nanoseconds on the TX datapath for 10G
operations.
• Bits 15:0—adjustment period in
fractional nanoseconds.
• Bits 31:16—reserved. Set these bits to 0.
Configure this register before you enable
the MAC IP core for operations.
RW 0x0
0x0104 tx_ns_adjustment_10G Static timing adjustment in nanoseconds
on the TX for 10G operations.
• Bits 15:0—adjustment period in
nanoseconds.
• Bits 31:16—reserved. Set these bits to 0.
Configure this register before you enable
the MAC IP core for operations.
RW 0x0
0x0108 tx_period_mult_speed
Specifies the clock period for timestamp
adjustment on the TX datapath for 10M/
100M/1G operations. The MAC IP core
multiplies the value of this register by the
number of stages separating the actual
timestamp and GMII/MII bus.
• Bits 15:0—period in fractional
nanoseconds.
• Bits 19:16—period in nanoseconds.
• Bits 31:20—reserved. Set these bits to 0.
The default value is 8 ns for 125 MHz
clock. Configure this register before you
enable the MAC IP core for operations.
RW
0x80000
UG-01144
2014.12.15
TX Timestamp Registers
4-19
Configuration Registers for LL Ethernet 10G MAC
Altera Corporation
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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