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Date Version Changes
December 2014 2014.12.15
• Updated the Performance and Resource Utilization table—improved
the resource utilization for IEEE 1588v2 feature.
• Added a new feature—10GBASE-R register mode:
• Added a new parameter—Enable 10GBASE-R register mode.
• Added new signals—tx_xcvr_clk, rx_xcvr_clk, xgmii_tx_
valid, xgmii_rx_valid.
• Added new parameter options for Time of Day Format.
• Added a new table in the Frame Type Checking topic to describe the
MAC behavior for different frame types.
• Added a new table—Register Access Type Convention—to describe
the access type for the IP core registers.
• Added a new section about timing constraints.
• Revised the receive timestamp registers word offset to start from
0x0120 to 0x012C.
• Added a recommendation for the csr_rst_n signal—deassert the
csr_rst_n signal at least once after tx_clk and rx_clk are stable.
• Revised the number of bits for fractional number of clock cycle for
rx_path_delay_10g_data and rx_path_delay_1g_data signals to
Bit [9:0]: Fractional number of clock cycle, Bit [21/15:10]:Number of
clock cycle.
• Updated the signals description for:
• tx_egress_timestamp_request_fingerprint[]
• tx_egress_timestamp_96b_data[]
• tx_egress_timestamp_64b_data[]
• tx_time_of_day_96b_1g_data
• tx_time_of_day_64b_1g_data
A-2
Low Latency Ethernet 10G MAC User Guide Document Revision History
UG-01144
2014.12.15
Altera Corporation
Additional Information
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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