Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manual do Utilizador descarregar pdf (Página 32)

Clock Requirements for 40GBASE-KR4 Variations on page 2-21

External TX MAC PLL on page 2-21

Placement Settings for the Low Latency 40-100GbE IP Core on page 2-21

Pin Assignments

When you integrate your Low Latency 40-100GbE IP core instance in your design, you must make

appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for

top-level signals while you are simulating and not ready to map the design to hardware.

For the Arria 10 device family, you must configure a transceiver PLL that is external to the 40-100GbE IP

core. The transceiver PLLs you configure are physically present in the device transceivers, but the LL

40-100GbE IP core does not configure and connect them. The required number of transceiver PLLs

depends on the distribution of your Ethernet data pins in the different Arria 10 transceiver blocks.

Related Information

• External Transceiver PLL Required in Arria 10 Designs on page 2-19

• Quartus II Help

For information about the Quartus II software, including virtual pins and the IP Catalog.

External Transceiver Reconfiguration Controller Required in Stratix V Designs

Low Latency 40-100GbE IP cores that target Stratix V devices require an external reconfiguration

controller to compile and to function correctly in hardware. Low Latency 40-100GbE IP cores that target

Arria 10 devices include a reconfiguration controller block in the PHY component and do not require an

external reconfiguration controller.

You can use the IP Catalog to generate an Altera Transceiver Reconfiguration Controller.

When you configure the Altera Transceiver Reconfiguration Controller, you must specify the number of

reconfiguration interfaces. The number of reconfiguration interfaces required for the Low Latency 40GbE

and 100GbE IP cores depends on the IP core variation.

Table 2-5: Number of Reconfiguration Interfaces

Lists the number of reconfiguration interfaces you should specify for the Altera Transceiver Reconfiguration

Controller for your Stratix V Low Latency 40-100GbE IP core. Low Latency 40-100GbE IP cores that target Arria

10 devices include a reconfiguration controller block in the PHY component and do not require any external

reconfiguration controllers.

PHY Configuration Number of Reconfiguration Interfaces

LL 40GbE (4x10.3125 lanes) 8

LL 100GbE (10x10.3125 lanes) 20

You can configure your reconfiguration controller with additional interfaces if your design connects with

multiple transceiver IP cores. You can leave other options at the default settings or modify them for your

preference.

You should connect the reconfig_to_xcvr, reconfig_from_xcvr, and reconfig_busy ports of the Low

Latency 40-100GbE IP core to the corresponding ports of the reconfiguration controller.

2-18

Pin Assignments

UG-01172

2015.05.04

Altera Corporation

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