Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manual do Utilizador Página 191
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Date Compatible ACDS
Version
Changes
• Clarified that IP core does not generate frames of eight bytes or less.
• Added waveform to illustrate register access on the control and
status interface, in the Control and Status Interface section
• Updated Differences Between Low Latency 40-100GbE IP Core and
40-100GbE IP Core v14.1 appendix with information about the
v14.1 IP core.
• Corrected misinformation about the IP core variations that support
the Enable TX CRC insertion parameter. Only IP core variations
that do not support flow control provide this parameter.
• Corrected order of TX_PFC_DADDRH (offset 0x60E) and TX_PFC_
DADDRL (offset 0x60D) registers.
• Corrected order of TX_PFC_SADDRH (offset 0x610) and TX_PFC_
SADDRL (offset 0x60F) registers.
• Corrected description of RX_PAUSE_DADDR registers at offsets 0x707
and 0x708. These registers are the same for standard flow control
and for priority-based flow control.
• Corrected installation directory figure for Stratix V variations, in
Installation and Licensing for LL 40-100GbE IP Core for Stratix V
Devices.
• Corrected erroneous indication that the value in RETRANSMIT_
XOFF_HOLDOFF_EN at offset 0x607 is indexed by the value in the TX_
PAUSE_QNUMBER register. In fact, the RETRANSMIT_XOFF_HOLDOFF_
EN register includes one bit for every flow-control priority queue
(one bit in case of standard flow control). Change is in Pause
Registers section.
• Fixed assorted typos and minor errors.
2014.08.18
14.0 and 14.0
Arria 10 Edition
• Updated for new Quartus II IP Catalog, which replaces the
MegaWizard Plug-In Manager starting in the Quartus II sofware
v14.0. Changes are located primarily in Getting Started chapter.
Reordered the chapter to accommodate the new descriptions.
• Updated the Installation section to clarify that the LL 40-100GbE IP
core v14.0 is available from the Self-Service Licensing Center, and
the LL 40-100GbE IP core v14.0 Arria 10 Edition is included in the
Quartus II software installation.
• Added new, additional allowed value for PHY reference clock
frequency: 322.265625 MHz.
• Added new parameter option to configure an inter-packet gap of 8.
• Added new parameter option to configure the IP core without
adapters, exposing a custom streaming client interface that is
narrower than the Avalon-ST interface. This option is available in
IP cores configured without a 1588 PTP module and without an
internal flow control scheme. You must select the custom streaming
client interface or the Avalon-ST client interface. Your selection
applies to both the RX and TX client interfaces.
UG-01172
2015.05.04
Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User
Guide Revision History
D-5
Additional Information
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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