Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manual do Utilizador descarregar pdf (Página 130)

Address Name Bit Description HW

Reset

Value

Access

0x507

MAC_CRC_

CONFIG

[0] The RX CRC forwarding configuration register.

Possible values are:

• 1’b0: remove RX CRC— do not forward it to the

RX client interface.

• 1’b1: retain RX CRC—forward it to the RX

client interface.

In either case, the IP core checks the incoming RX

CRC and flags errors.

1’b0 RW

0x50A CFG_PLEN_

CHECK

[0] Enables payload length checking. If you set this bit

to the value of 1, bit[4] of the rx_error signal flags

any payload lengths that do not match the length

field.

Related Information

Link Fault Signaling Registers on page 3-70

Describes the fault link signaling and fault status signal registers.

Pause Registers

The pause registers together with the pause signals implement the pause functionality defined in the IEEE

802.3ba-2010 100G Ethernet Standard. You can program the pause registers to control the insertion and

decoding of pause frames, to help reduce traffic in congested networks.

Table 3-26: TX Ethernet Flow Control (Pause Functionality) Registers

Some registers are different depending on whether you select Standard flow control or Priority-based flow

control in the Low Latency 40-100GbE parameter editor. Where the difference is only whether the register refers

to the single standard flow control priority class or whether distinct bits in the register refer to the individual

priority queues, the two uses are documented together. In that case we understand that standard flow control

effectively supports a single priority queue.

When your IP core implements priority-based flow control, the following registers provide an access window into

an internal table of values, one per priority queue. The entry currently accessible in the registers is determined by

the value you write to the TX_PAUSE_QNUMBER register.

• RETRANSMIT_XOFF_HOLDOFF_QUANTA at offset 0x608

• TX_PAUSE_QUANTA at offset 0x609

Addr Name Bit Description HW Reset

Value

Access

0x600 TXSFC_REVID [31:0] TX standard flow control module revision

ID.

0x01282014 RO

0x601 TXSFC_

SCRATCH

[31:0] Scratch register available for testing. 32'b0 RW

UG-01172

2015.05.04

Pause Registers

3-85

Functional Description

Altera Corporation

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