Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manual do Utilizador Página 141
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Address Name- Description Access
0x827 CNTR_TX_MCAST_
DATA_OK_HI
Number of valid multicast frames transmitted, excluding
control frames (upper 32 bits)
RO
0x828 CNTR_TX_BCAST_
DATA_OK_LO
Number of valid broadcast frames transmitted, excluding
control frames (lower 32 bits)
RO
0x829 CNTR_TX_BCAST_
DATA_OK_HI
Number of valid broadcast frames transmitted, excluding
control frames (upper 32 bits)
RO
0x82A CNTR_TX_UCAST_
DATA_OK_LO
Number of valid unicast frames transmitted, excluding
control frames (lower 32 bits)
RO
0x82B CNTR_TX_UCAST_
DATA_OK_HI
Number of valid unicast frames transmitted, excluding
control frames (upper 32 bits)
RO
0x82C CNTR_TX_MCAST_
CTRL_LO
Number of valid multicast frames transmitted, excluding
data frames (lower 32 bits)
RO
0x82D CNTR_TX_MCAST_
CTRL_HI
Number of valid multicast frames transmitted, excluding
data frames (upper 32 bits)
RO
0x82E CNTR_TX_BCAST_
CTRL_LO
Number of valid broadcast frames transmitted, excluding
data frames (lower 32 bits)
RO
0x82F CNTR_TX_BCAST_
CTRL_HI
Number of valid broadcast frames transmitted, excluding
data frames (upper 32 bits)
RO
0x830 CNTR_TX_UCAST_
CTRL_LO
Number of valid unicast frames transmitted, excluding data
frames (lower 32 bits)
RO
0x831 CNTR_TX_UCAST_
CTRL_HI
Number of valid unicast frames transmitted, excluding data
frames (upper 32 bits)
RO
0x832 CNTR_TX_PAUSE_
LO
Number of valid pause frames transmitted (lower 32 bits) RO
0x833 CNTR_TX_PAUSE_
HI
Number of valid pause frames transmitted (upper 32 bits) RO
0x834 CNTR_TX_RUNT_LO Number of transmitted runt packets (lower 32 bits). The IP
core does not transmit frames of length less than nine bytes.
The IP core pads frames of length nine bytes to 64 bytes to
extend them to 64 bytes.
RO
0x835 CNTR_TX_RUNT_HI Number of transmitted runt packets (upper 32 bits). The IP
core does not transmit frames of length less than nine bytes.
The IP core pads frames of length nine bytes to 64 bytes to
extend them to 64 bytes.
RO
3-96
TX Statistics Registers
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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