Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manual do Utilizador descarregar pdf (Página 117)

Table 3-23: LL 40-100GbE IP Core 40GBASE-KR4 Registers and Register Fields Not in Arria 10 10GBASE-KR

PHY IP Core

Documents the differences between the Arria 10 10GBASE-KR PHY register definitions and the 40GBASE-KR4

registers of the LL 40-100GbE IP core. All 10GBASE-KR PHY registers and register fields not listed in the table are

available in the 40GBASE-KR4 variations of the LL 40-100GbE IP core.

The 10GBASE-KR PHY register listings are available in the 0xB0Arria 10 10GBASE-KR Registers appendix and

in the 10GBASE-KR PHY Register Defintions section of the 10GBASE-KR PHY IP Core section in the Arria 10

Transceiver PHY User Guide. The information in these two sources should be identical. Refer to Arria 10

10GBASE-KR Registers for details.

Where the 10GBASE-KR PHY register definitions list 10GBASE-R, substitute 40GBASE-KR4 with auto-negotia‐

tion and link training both turned off, and where the 10GBASE-KR PHY register definitions list 10GBASE-KR

(except in the description of 0xCB[24:0]), substitute 40GBASE-KR4. Where a register field description in the

10GBASE-KR PHY register definitions refers to link training or FEC in the single-lane 10GBASE-KR PHY IP

core, substitute link training or FEC on Lane 0 of the 40GBASE-KR4 IP core variation.

Registers and register bits not described in either location should be considered Reserved.

To modify a field value in any LL 40GBASE-KR4 specific register, whether an underlying 10GBASE-KR PHY IP

core register or one of the registers defined in this table, you must perform a read-modify-write operation to

ensure you do not modify the values of any other fields in the register.

Address Name Bit Description HW

Reset

Value

Access

0x0B0

SEQ Force

Mode[3:0]

[7:4]

Forces the sequencer to a specific protocol. Must

write the Reset SEQ bit (bit [0]) to 1 for the

Force to take effect. The following encodings are

defined:

• 0000: No force

• 0001: GigE mode (unsupported)

• 0010: XAUI mode (unsupported)

• 0100: 40GBASE-R4 mode (without auto-

negotiation and without link training)

• 0101: 40GBASE-KR4 mode

• 1100: 40GBASE-R4 mode with FEC (without

auto-negotiation and without link training)

4'b0

Enable Arria

Calibration

[8] When set to 1, it enables the Arria 10 HSSI

reconfiguration calibration as part of the PCS

dynamic reconfiguration. 0 skips the calibration

when the PCS is reconfigured.

1'b1 RW

Reserved [17] Reserved

Access FEC error indication selection using the

Arria 10 dynamic reconfiguration interface.

Refer to the descriptions of register 0xB2.

Reserved

[19]

Reserved

3-72

LL 40GBASE-KR4 Registers

UG-01172

2015.05.04

Altera Corporation

Functional Description

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