Altera Cyclone II DSP Development Board Manual do Utilizador Página 37
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Altera Corporation Reference Manual 2–29
August 2006 Cyclone II DSP Development Board
Cyclone II DSP Development Board Components
Table 2–21 lists the DDR2 SRAM DIMM pin-outs for the EP2C70F672
FPGA.
Table 2–21. DDR2 SDRAM DIMM Pin-Outs (Part 1 of 8) Note (1)
Cyclone II (U12)
Signal Name (2)
DIMM (J8) Signal
Name (2)
DIMM (J8) Pin
Number
Cyclone II (U12)
Pin Number
DIMM_A_R0 DIMM_A0 188 AE4
DIMM_A_R1 DIMM_A1 183 AC8
DIMM_A_R2 DIMM_A2 63 AD6
DIMM_A_R3 DIMM_A3 182 Y10
DIMM_A_R4 DIMM_A4 61 AF5
DIMM_A_R5 DIMM_A5 60 AD7
DIMM_A_R6 DIMM_A6 180 AC6
DIMM_A_R7 DIMM_A7 58 AB8
DIMM_A_R8 DIMM_A8 179 AD5
DIMM_A_R9 DIMM_A9 177 AE11
DIMM_A_R10 DIMM_A10 70 AE5
DIMM_A_R11 DIMM_A11 57 AD4
DIMM_A_R12 DIMM_A12 176 Y12
DIMM_A_R13 DIMM_A13 196 AF7
DIMM_A_R14 DIMM_A14 174 AC5
DIMM_A_R15 DIMM_A15 173 AF13
DIMM_BA_R0 DIMM_BA0 71 Y18
DIMM_BA_R1 DIMM_BA1 190 AF23
DIMM_BA_R2 DIMM_BA2 54 AB15
DIMM_CASN DIMM_CASN 74 AC22
DIMM_CK_N0 DIMM_CK_N0 186 AD19
DIMM_CK_N1 DIMM_CK_N1 138 AD21
DIMM_CK_N2 DIMM_CK_N2 221 AA20
DIMM_CK_P0 DIMM_CK_P0 185 AC21
DIMM_CK_P1 DIMM_CK_P1 137 AB20
DIMM_CK_P2 DIMM_CK_P2 220 AD22
DIMM_CKE_R0 DIMM_CKE0 52 AE21
DIMM_CKE_R1 DIMM_CKE1 171 AC19
DIMM_CSN_R0 DIMM_CSN0 193 AF22
DIMM_CSN_R1 DIMM_CSN1 76 AB18
- Reference Manual 1
- MNL-CII012805-1.1 2
- Contents 3
- About This Manual 5
- Typographic 6
- Conventions 6
- Chapter 1. Introduction 7
- Features Overview 8
- Chapter 2. Cyclone II DSP 9
- Development 9
- Board Components 9
- Components & Interfaces 10
- USER EPCS (U36) 11
- (Flash Memory) 11
- Expansion Connectors 13
- General Connectors 13
- DIMM_SYNC_CLK) is a 14
- CONFIG_DONEn is asserted) 15
- Featured Device 17
- User Interfaces 17
- Closed Position 19
- Open Position 19
- USER_PB3 AE14 20
- USER_PB2 AE22 20
- USER_PB1 AE16 20
- USER_PB0 AC18 20
- Audio CODEC Converter (U11) 22
- Audio Jacks (J10, J14, J16) 22
- VGA Output Connector (J21) 23
- D/A Converter (U25 & U30) 25
- D/A Converter Clocks 26
- CLK_OSC_DACA (Channel A) 27
- CLK_OSC_DACB (Channel B) 27
- FPGA_TO_DAC_CLK 27
- SMA_TO_DAC_CLK 27
- Note to Table 2–13: 28
- A/D Converter (U26 & U31) 30
- A/D Converter Clocks 31
- CLK_OSC_ADCA (Channel A) 32
- CLK_OSC_ADCB (Channel B) 32
- FPGA_TO_ADC_CLK 32
- SMA_TO_ADC_CLK 32
- Note to Table 2–18: 33
- Components 34
- DDR2 SDRAM DIMM Clocks 35
- Memory Components 36
- Note to Figure 2–12: 36
- EPCS Select (J29) 45
- Synchronous SRAM Device (U22) 47
- Note to Table 2–23: 49
- ■ EVM_CEn2 selects the SSRAM 50
- J15Pin 1 51
- Pin 1 Pin 1 51
- Notes to Figure 2–16: 52
- Note to Table 2–24: 55
- General 58
- Connectors 58
- Mictor Connector (J12) 61
- Notes to Figure 2–19: 62
- Note to Table 2–28: 64
- Status LEDs & 65
- Reset/Power 65
- Switches 65
- USER RESET 66
- SYS RESET 66
- Clock Circuitry 67
- Setting the Clocks 68
- CLK SMA Connector (J17) 69
- Clock Buffer (U16) 71
- Power Supply 72
- Power Plane 78
- Supplies 78
- Settings 78
- Appendix A. DDR2 SDRAM 79
- DIMM Connector Pin Out Table 79
- DIMM_DQS5 C12 C12 82
- DIMM_DQS6 B14 B14 82
- DIMM_DQS7 C17 C17 82
- DIMM_DQS8 B6 B6 82
- Appendix B. SSRAM 83
- Pin-Out Table 83
- Note to Ta ble B –1: 85
- Appendix C. Cyclone II EP2C70 87
- Device Pin-Out Table 87
- Appendix D. Restoring the 109
- Factory Design 109
- SAFE/USER Mode 110
- ASI Connector 111
- JTAG Cable 111
- Introduction 112
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