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2–28 Reference Manual Altera Corporation

Cyclone II DSP Development Board August 2006

Memory Components

Figure 2–12. DDR2 SDRAM DIMM Clocking Diagram Note (1)

Note to Figure 2–12:

(1) One DDR register consists of one I/O register, one core register, and one output multiplexer.

(2) See Figure 2–21, "Cyclone II DSP Development Board Clocking Options" for timing source inforamtion.

DDR Out

Reg

O E Out

Reg

DDR Out

Reg

O E Out

Reg

DDR Out

Reg

DDR In

Reg

Preamble

control

Delay

control

Non-I/O-Related

Logic

EP2C35F672 FPGA

DIMM_CK_P0

DIMM_CK_P1

DIMM_CK_P2

DIMM_CK_N1

DIMM_CK_N0

DIMM_CK_N2

DIMM_DQ(71:0)

DIMM_DQS(8:0)

DDR2 SDRAM DIMM

-90˚ shift

0˚ shift

2ns˚ shift

DQS In

DQS Out

delay_val

PLL

IN 0

Timing Source (2)

IN 1

CLKIN_TOP or CLKIN_BOT

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 111 112

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