Altera CPRI v6.0 MegaCore Function Manual do Utilizador Página 99
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Bits Field Name Type Value on
Reset
Description
10:8 state_
startup_
seq
RO 3'b0 Indicates the current state of the start-up sequence. This field
has the following valid values:
• 3'b000: State A: Standby
• 3'b001: State B: L1 Synchronization
• 3'b011: State C: Protocol Setup
• 3'b010: State D: Control and Management Setup
• 3'b110: State E: Interface and VSS Negotiation
• 3'b111: State F: Operation
• 3'b101: State G: Passive Link
7:4 Reserved UR0 4'b0
3 nego_vss_
complete
RW 1'b0 Indicates the Vendor Specific negotiation is complete. You
must set this bit to move the start-up sequence state machine
from state E to state F. If you turn on Enable start-up sequence
state machine, the nego_vss_complete input signal writes
directly to this register bit.
2 nego_cm_
complete
RW 1'b0 Indicates the Control and Management negotiation is complete
and the start-up sequence state machine can move from state D
to state E. If the slow_cm_rate_auto field or the fast_cm_ptr_
auto field, or both, in the CM_CONFIG register has the value of 1,
the IP core updates this bit if the user does not update it.
If you turn on Enable start-up sequence state machine, the
nego_cm_complete input signal writes directly to this register
bit.
1 nego_
protocol_
complete
RW 1'b0 Indicates the protocol version negotiation is complete and the
start-up sequence state machine can move from state C to state
D. If the prot_ver_auto field of the PROT_VER register has the
value of 1, the IP core updates this bit if the user does not
update it.
If you turn on Enable start-up sequence state machine, the
nego_protocol_complete input signal writes directly to this
register bit.
0 nego_
bitrate_
complete
RW 1'b0 Indicates the CPRI line bit rate negotiation is complete.
If you turn on Enable start-up sequence state machine, the
nego_bitrate_complete input signal writes directly to this
register bit.
START_UP_TIMER Register
5-10
START_UP_TIMER Register
UG-01156
2015.02.16
Altera Corporation
CPRI v6.0 IP Core Registers
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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