Altera CPRI v6.0 MegaCore Function Manual do Utilizador Página 46
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Figure 3-9: AUX TX Timing Diagram with Error
Illustrates the behavior of the aux_tx_err signal on the AUX TX interface of a CPRI v6.0 IP core running
at 0.6144 Gbps. The aux_tx_ctrl signal shows that when aux_tx_seq has the value of zero, the first byte
at the corresponding position in the target CPRI frame is a control byte. The value of the Auxiliary latency
cycle(s) parameter is zero. Therefore, the data on aux_tx_data is delayed by one clock cycle from the
value on aux_tx_seq. The data that appears on aux_tx_data when aux_tx_seq has the value of 1 is the
data that targets position X.Y.Z.0 in the target CPRI frame.
The value of Mask #1 is presumably 0xFFXXXXXX, indicating that the incoming data on aux_tx_data is
intended to overwrite this control byte in the target CPRI frame. Therefore, in the following cpri_clkout
cycle, the IP core asserts the aux_tx_err signal.
4095 0
0
3
255 1
149 0
2 0 1 2 3 0 1 2
X Data #1 Data #2 Data #3 Data #4 Data #5
cpri_clkout
aux_tx_rfp
aux_tx_bfn
aux_tx_hfp
aux_tx_hfn
aux_tx_x
aux_tx_seq
aux_tx_data
aux_tx_mask
Auxiliary latency cycle(s) == 0
Data #6
X Mask #1 Mask #2 Mask #3 Mask #4 Mask #5 Mask #6
0000 1000 0000 1000 0000
aux_tx_err
aux_tx_ctrl[3:0]
Related Information
• AUX Interface Synchronization on page 3-17
Illustrates the relationship between the AUX synchronization signals.
• Auxiliary Latency Cycles on page 3-17
The Auxiliary latency cycle(s) parameter affects the relative timing of the data on the aux_tx_data and
aux_tx_mask busses. This section provides an explanation of the parameter's effect and purpose.
3-16
AUX Interface Signals
UG-01156
2014.08.18
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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