Altera DDR Timing Wizard Manual do Utilizador

101 Innovation DriveSan Jose, CA 95134http://www.altera.comDDR Timing WizardUG-DDRTMNG-3.0Document Version: 3.0Document Date: November 2007User Guide

1–4 Altera CorporationDDR Timing Wizard User Guide November 2007Introduction1 Critical resynchronization register placement constraints provided by th

Altera Corporation 1–5November 2007 DDR Timing Wizard User GuideAbout the DDR Timing WizardFigure 1–1 shows the typical Quartus II external memory de

1–6 Altera CorporationDDR Timing Wizard User Guide November 2007FeaturesFeaturesThe DDR Timing Wizard has the capability to: Constrain a design with

Altera Corporation 2–1November 20072. Getting StartedSystem and Software RequirementsThe instructions in this section require Quartus II software ver

2–2 Altera CorporationDDR Timing Wizard User Guide November 2007Design Flow1 You do not need to remove these location assignments when using DTW even

Altera Corporation 2–3November 2007 DDR Timing Wizard User GuideGetting Startedthe names of the PLL clocks and registers (as needed) for the timing r

2–4 Altera CorporationDDR Timing Wizard User Guide November 2007Design Flowstandard as the CK/CK# pins, and are placed on the same side as the DQS/DQ

Altera Corporation 2–5November 2007 DDR Timing Wizard User GuideGetting Started1 You need to insert intermediate resynchronization registers when you

2–6 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWFigure 2–2. Launching the DDR Timing Wizard3. Cl

Altera Corporation 2–7November 2007 DDR Timing Wizard User GuideGetting Started1 You do not need to perform Quartus II Analysis and Synthesis the fir

ii Altera Corporation101 Innovation DriveSan Jose, CA 95134www.altera.comTechnical Support:www.altera.com/support/Literature Services:literature@alte

2–8 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWFigure 2–3. First Page of the DDR Timing Wizard—

Altera Corporation 2–9November 2007 DDR Timing Wizard User GuideGetting StartedFigure 2–4. Page 2 of the DTW—Confirm the Project Directory and Revisi

2–10 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWFigure 2–5. Page 3 of the DTW—Importing Data fr

Altera Corporation 2–11November 2007 DDR Timing Wizard User GuideGetting Started1 The DTW can extract the names of PLL clocks, PLL phase shifts, and

2–12 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWFigure 2–7. Timing Assignments to be Added to t

Altera Corporation 2–13November 2007 DDR Timing Wizard User GuideGetting StartedIf DTW failed to extract PLL clock information during the import step

2–14 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWAfter entering the resynchronization clock name

Altera Corporation 2–15November 2007 DDR Timing Wizard User GuideGetting Started4. Page 3 asks if you want to import data from the legacy controller

2–16 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWFigure 2–9. Select Memory Type6. Select the app

Altera Corporation 2–17November 2007 DDR Timing Wizard User GuideGetting Started1 If you do not find your memory device in the pull-down menu, select

Altera Corporation iiiNovember 2007Table of ContentsAbout this User Guide ...

2–18 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWFigure 2–11. Specify DQS PinsYou can either man

Altera Corporation 2–19November 2007 DDR Timing Wizard User GuideGetting StartedIf you have not performed Analysis and Synthesis on the design, the N

2–20 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWFigure 2–13. Selecting the DQS PinsFigure 2–14.

Altera Corporation 2–21November 2007 DDR Timing Wizard User GuideGetting Startedb. The DQS pins are now displayed in the DTW GUI (Figure 2–15). Figur

2–22 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTW1 The postamble register name from the Altera D

Altera Corporation 2–23November 2007 DDR Timing Wizard User GuideGetting Started9. Identify the CK and CK# pins. The Altera DDR/DDR2 SDRAM Controller

2–24 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTW10. Identify the address and control pins. The

Altera Corporation 2–25November 2007 DDR Timing Wizard User GuideGetting Startedf Refer to Appendix A of the DDR and DDR2 SDRAM Controller Compiler U

2–26 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTW1 The default TimeQuest Timing Analyzer clockin

Altera Corporation 2–27November 2007 DDR Timing Wizard User GuideGetting StartedFigure 2–20. Fedback Resynchronization Path (Highlighted)The first fi

iv Altera CorporationNovember 2007Table of Contents DDR Timing Wizard User GuideChanging Clock Phase Shift ...

2–28 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWf Refer to AN 413: Using Legacy Integrated Stat

Altera Corporation 2–29November 2007 DDR Timing Wizard User GuideGetting StartedFigure 2–21. Resynchronization Clock and Phase Shift Relationship in

2–30 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWwith the –auto_adjust_cycles option, the DTW wi

Altera Corporation 2–31November 2007 DDR Timing Wizard User GuideGetting StartedFigure 2–22. Postamble Clock ConnectivityThe postamble_sys_cycle and

2–32 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWTable 2–2 shows the relationship between the le

Altera Corporation 2–33November 2007 DDR Timing Wizard User GuideGetting StartedFigure 2–23. Postamble Clock and Phase Shift Relationship in DTW and

2–34 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWYou also must specify which PLL output clock dr

Altera Corporation 2–35November 2007 DDR Timing Wizard User GuideGetting StartedDTW requires the following numbers to be entered:● Nominal memory to

2–36 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTW● Skew between wires in an address/control grou

Altera Corporation 2–37November 2007 DDR Timing Wizard User GuideGetting StartedFigure 2–26. FPGA Timing Parameters When Using TimeQuest Timing Analy

Altera Corporation vNovember 2007 PreliminaryAbout this User GuideRevision HistoryThe table below displays the revision history for the chapters in

2–38 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWFigure 2–27. FPGA Timing Parameters Page When U

Altera Corporation 2–39November 2007 DDR Timing Wizard User GuideGetting Startedwhile in HardCopy II, these numbers need to be calculated separately

2–40 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWWhen you check the option to use Both fast and

Altera Corporation 2–41November 2007 DDR Timing Wizard User GuideGetting Startedgenerates two .tcl files with a .fast and .slow extensions to indicat

2–42 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWFigure 2–29. Last Page of DTW with Separate Tim

Altera Corporation 2–43November 2007 DDR Timing Wizard User GuideGetting Startedtiming results from the Quartus II Classic Timing Analyzer. This mess

2–44 Altera CorporationDDR Timing Wizard User Guide November 2007Entering and Editing Inputs to the DTWFigure 2–31. Last Page of the DTW When Using Ti

Altera Corporation 2–45November 2007 DDR Timing Wizard User GuideGetting StartedAfter you click Finish, your project should have the following assign

2–46 Altera CorporationDDR Timing Wizard User Guide November 2007DTW Limitations1 You can use a similar resynchronization scheme like DDR/DDR2 interfa

Altera Corporation 2–47November 2007 DDR Timing Wizard User GuideGetting Started When using the DDR/DDR2 SDRAM core version 3.4.0 and Quartus II ver

vi Altera CorporationPreliminary November 2007Typographic Conventions DDR Timing Wizard User GuideTypographic ConventionsThis document uses the typog

2–48 Altera CorporationDDR Timing Wizard User Guide November 2007DTW Limitations

Altera Corporation 3–1November 20073. Using thedtw_timing_analysis.tclScriptIntroductionIf your design does not meet timing, you must know how to opt

3–2 Altera CorporationDDR Timing Wizard User Guide November 2007IntroductionFigure 3–1 shows the general algorithm of the dtw_timing_analysis.tcl. Fig

Altera Corporation 3–3November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptRunning dtw_timing_analysis.tcl ScriptTo run

3–4 Altera CorporationDDR Timing Wizard User Guide November 2007Introduction-after_iptb <value>import Instructs the script to analyze and elabor

Altera Corporation 3–5November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl Script-ignore_moveNone Allows the script to run eve

3–6 Altera CorporationDDR Timing Wizard User Guide November 2007Introduction4. Open the Compilation Report panel by clicking on Compilation Report und

Altera Corporation 3–7November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptFigure 3–2. Script Results as Part of Timing

3–8 Altera CorporationDDR Timing Wizard User Guide November 2007Introductionf For more information on the different implementations available in Strat

Altera Corporation 3–9November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptThe PLL name column shows which PLL clock tap

Altera Corporation 1–1November 20071. About the DDR TimingWizardRelease Information Table 1–1 shows the first Quartus® II software version that suppo

3–10 Altera CorporationDDR Timing Wizard User Guide November 2007IntroductionTable 3–3 shows the default clock names and usage if you are using the Al

Altera Corporation 3–11November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptWhen you must change a PLL output phase shif

3–12 Altera CorporationDDR Timing Wizard User Guide November 2007Timing Closure Process What To Do NextThis panel shows how to proceed in the design.

Altera Corporation 3–13November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptFigure 3–6. Timing Closure ProcessNote to Fi

3–14 Altera CorporationDDR Timing Wizard User Guide November 2007Timing Closure ProcessTiming Closure Differences in DDR2/DDR SDRAM, QDRII+/QDRII SRAM

Altera Corporation 3–15November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptRLDRAM II InterfacesIn RLDRAM II interfaces,

3–16 Altera CorporationDDR Timing Wizard User Guide November 2007Timing Closure ProcessFor RLDRAM II designs created in Quartus II version 7.2 and hig

Altera Corporation 3–17November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptFigure 3–8. Initial Resynchronization, Posta

3–18 Altera CorporationDDR Timing Wizard User Guide November 2007Timing Closure Processand hold time requirements of the user logic clocked by the sys

Altera Corporation 3–19November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptExtract tcos button in DTW or use the –extra

1–2 Altera CorporationDDR Timing Wizard User Guide November 2007Device Family SupportDevice Family SupportThe DTW Tcl script provides full support for

3–20 Altera CorporationDDR Timing Wizard User Guide November 2007Timing Closure Processdedicated PLL output for your address/command clock or to add y

Altera Corporation 3–21November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptFigure 3–10. Modified Project Settings Windo

3–22 Altera CorporationDDR Timing Wizard User Guide November 2007Timing Closure Process1 Note that if only 1 or 2 pins fail timing, you can adjust the

Altera Corporation 3–23November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptFor actual steps on how to change the phase

3–24 Altera CorporationDDR Timing Wizard User Guide November 2007Timing Closure Processb. Open the <project_name>.v/.vhd to check which clock is

Altera Corporation 3–25November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl Scriptii. Open the altpll MegaWizard to modify the

3–26 Altera CorporationDDR Timing Wizard User Guide November 2007Timing Closure ProcessFigure 3–13. Recommendation Setting To Change Clock Cycle Selec

Altera Corporation 3–27November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptYou can then use the -auto_adjust_cycles swi

3–28 Altera CorporationDDR Timing Wizard User Guide November 2007Timing Closure ProcessIn the DTW, however, if you create a 2-PLL mode memory interfac

Altera Corporation 3–29November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptFigure 3–15. Preparing for Dedicated Address

Altera Corporation 1–3November 2007 DDR Timing Wizard User GuideAbout the DDR Timing Wizard1 The new ALTMEMPHY megafunction, introduced in Quartus II

3–30 Altera CorporationDDR Timing Wizard User Guide November 2007Timing Closure Process1 The MegaWizard inverts the address/command clock in a lower-l

Altera Corporation 3–31November 2007 DDR Timing Wizard User GuideUsing the dtw_timing_analysis.tcl ScriptTo avoid assigning these resynchronization r

3–32 Altera CorporationDDR Timing Wizard User Guide November 2007ConclusionConclusionYou can close timing within two compiles if you do not need to ch