Altera CPRI v6.0 MegaCore Function Manual do Utilizador Página 12
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Getting Started with the CPRI v6.0 IP Core
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2014.08.18
UG-01156
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Explains how to install, parameterize, and simulate the Altera CPRI v6.0 IP core.
Installation and Licensing on page 2-2
The CPRI v6.0 IP core is an extended IP core which is not included with the Quartus II release. This
section provides a general overview of the Altera extended IP core installation process to help you quickly
get started with any Altera extended IP core.
Specifying IP Core Parameters and Options on page 2-2
After you install and integrate the extended IP core in the ACDS release, the CPRI v6.0 IP core supports
the standard customization and generation process. This IP core does not generate a testbench or example
design simultaneously with generation of the IP core. Instead, you must use the Example Design button in
the CPRI v6.0 parameter editor to generate the testbench. This IP core is not supported in Qsys.
Files Generated for Altera IP Cores on page 2-3
The Quartus software generates the following IP core output file structure.
CPRI v6.0 IP Core Parameters on page 2-7
The CPRI v6.0 parameter editor provides the parameters you can set to configure the CPRI v6.0 IP core
and simulation testbench.
Integrating Your IP Core in Your Design: Required External Blocks on page 2-11
You must connect your CPRI v6.0 IP core to some additional required design components. Your design
can compile without some of these connections and logical blocks, but it will not function correctly in
hardware unless all of them are present and connected in your design.
Simulating Altera IP Cores on page 2-16
The Quartus II software supports RTL- and gate-level design simulation of Altera IP cores in supported
EDA simulators. Simulation involves setting up your simulator working environment, compiling
simulation model libraries, and running your simulation.
Understanding the Testbench on page 2-17
Altera provides a demonstration testbench with the CPRI v6.0 IP core.
Running the Testbench on page 2-17
To run the Altera CPRI v6.0 IP core demonstration testbench, follow these steps.
Related Information
Managing Quartus II Projects
Refer to the "Integrating IP Cores" section of this Quartus II Handbook chapter for more information
about generating an Altera IP core and integrating it in your Quartus II project.
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2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
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101 Innovation Drive, San Jose, CA 95134
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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