Altera CPRI v6.0 MegaCore Function Manual do Utilizador Página 18
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CPRI v6.0 IP Core Parameters
The CPRI v6.0 parameter editor provides the parameters you can set to configure the CPRI v6.0 IP core
and simulation testbench.
Table 2-2: General CPRI v6.0 IP Core Parameters
Describes the general parameters for customizing the CPRI v6.0 IP core. These parameters appear on the General
tab in the CPRI v6.0 parameter editor.
Parameter Range Default
Setting
Parameter Description
Bit rate (Mbits/s) • 614.4
• 1228.8
• 2457.6
• 3072.0
• 4915.2
• 6144.0
• 9830.4
• 10137.6
614.4 Selects the CPRI line bit rate.
Arria V GZ devices support all line bit rates except
10.1376 Gbps. All other supported devices support
all CPRI line bit rates.
Operation mode • Master
• Slave
Master
Specifies whether the CPRI v6.0 IP core is
configured as a CPRI link master or a CPRI link
slave.
The value of this parameter determines the initial
and reset operation mode of the CPRI v6.0 IP core.
You can modify the IP core operation mode
dynamically by modifying the value of the
operation_mode field of the L1_CONFIG register.
Supported receiver
CDR frequency
(MHz)
Per drop-down
menu
307.2
Specifies the incoming reference clock frequency
for the receiver CDR PLL, in MHz.
You must drive the input clock xcvr_cdr_refclk
at the frequency you specify for this parameter.
UG-01156
2014.08.18
CPRI v6.0 IP Core Parameters
2-7
Getting Started with the CPRI v6.0 IP Core
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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