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manuais Altera Arria V Avalon-MM

Manuais de instruções e guias do utilizador para Instrumentos de medida Altera Arria V Avalon-MM.
Disponibilizamos 1 manuais Altera Arria V Avalon-MM em pdf para descarga gratuita: Manual do Utilizador


Altera Arria V Avalon-MM Manual do Utilizador (166 páginas)


Marca: Altera | Categoria: Instrumentos de medida | Tamanho: 1.66 MB |

 

Índice

User Guide

1

Datasheet

2

Features

3

Release Information

6

Device Family Support

6

Altera FPGA

7

IP Core Verification

9

Debug Features

9

Recommended Speed Grades

10

Hard IP for PCI Express

12

Running Qsys

13

Generating the Example Design

14

Programming a Device

18

Quartus II Programmer

19

Parameter Settings

20

Parameter Value Description

21

Device Capabilities

23

Error Reporting

24

Link Capabilities

25

MSI and MSI-X Capabilities

25

Power Management

27

Subscribe

31

RX Avalon-MM Master Signals

33

Clock Signals

38

Reset Signals

38

Signal Direction Description

39

Hard IP Status

40

IntxReq_i

44

IntAck_o

44

Hard IP Status Extension

46

Field and Bit Map

54

0134678951

54

Serial Interface Signals

55

9 Ch 18 Ch

56

Variant Data CMU Clock

57

PIPE Interface Signals

58

Test Signals

62

Registers

63

Altera-Defined VSEC Registers

71

CvP Registers

72

Address Range Register

76

Bit Name Access Description

77

Bits Name Access Description

78

PCI Express Mailbox Registers

79

Avalon-MM Mailbox Registers

83

Address Name Access

84

Description

84

Byte Offset

84

Register Dir Description

84

Sending a Write TLP

90

Root Port TLP Data Registers

92

Bits Register Description

95

Reset and Clocks

98

Example Design

99

UG-01105_avmm

100

2014.12.15

100

Clock Domains

102

Data Rate Frequency

103

Related Information

103

Clock Summary

104

Interrupts for Endpoints

105

MSI/MSI‑X Support

107

Qsys System

108

Error Handling

109

Physical Layer Errors

110

Data Link Layer Errors

110

Transaction Layer Errors

111

Error Type Description

112

Status Bit Conditions

115

IP Core Architecture

117

Hard IP for PCI Express

118

Clocks and Reset

119

Transceiver Reconfiguration

119

Interrupts

119

Data Link Layer

120

Altera Corporation

121

Send Feedback

121

Physical Layer

122

TX Packets

123

Avalon‑MM Bridge TLPs

127

Byte Enable Value Description

128

PCI Express Avalon-MM Bridge

130

RX Block

136

Avalon-MM RX Master Block

136

TX Block

137

Interrupt Handler Block

137

Design Implementation

139

Making Pin Assignments

140

Optional Features

141

ECRC on the RX Path

142

ECRC on the TX Path

143

Enable PLL calibration

145

Debugging

148

Setting Up Simulation

149

Use Third-Party PCIe Analyzer

150

BIOS Enumeration Issues

151

Address[31:2]

152

Figure A-6: I/O Read Request

154

7 6 5 4 3 2 1 0

158

Core Config 8 4 1

158

Additional Information

160

Date Version Changes Made

161

How to Contact Altera

163

Typographic Conventions

164

Visual Cue Meaning

165




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