Altera Arria 10 Avalon-ST Manual do Utilizador Página 98
- Página / 275
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
Table 6-6: Reset Signals
Signal Direction Description
npor
Input Active low reset signal. In the Altera hardware example designs,
npor is the OR of pin_perst and local_rstn coming from the
software Application Layer. If you do not drive a soft reset signal
from the Application Layer, this signal must be derived from
pin_perst. You cannot disable this signal. Resets the entire IP
Core and transceiver. Asynchronous.
This signal is edge, not level sensitive; consequently, you cannot
use a low value on this signal to hold custom logic in reset. For
more information about the reset controller, refer to Reset.
reset_status
Output Active high reset status signal. When asserted, this signal
indicates that the Hard IP clock is in reset. The reset_status
signal is synchronous to the pld_clk clock and is deasserted only
when the npor is deasserted and the Hard IP for PCI Express is
not in reset (reset_status_hip = 0). You should use reset_
status to drive the reset of your application. This reset is used
for the Hard IP for PCI Express IP Core with the Avalon-ST
interface.
pin_perst
Input Active low reset from the PCIe reset pin of the device. pin_perst
resets the datapath and control registers. Configuration via
Protocol (CvP) requires this signal. For more information about
CvP refer to Configuration via Protocol (CvP).
Arria 10 devices can have up to 4 instances of the Hard IP for
PCI Express. Each instance has its own pin_perst signal. You
must connect the pin_perst of each Hard IP instance to the
corresponding nPERST pin of the device. These pins have the
following locations:
• NPERSTL0: bottom left Hard IP and CvP blocks
• NPERSTL1: top left Hard IP block
• NPERSTR0: bottom right Hard IP block
• NPERSTR1: top right Hard IP block
For example, if you are using the Hard IP instance in the bottom
left corner of the device, you must connect pin_perst to
NPERSL0.
For maximum use of the Arria 10 device, Altera recommends
that you use the bottom left Hard IP first. This is the only
location that supports CvP over a PCIe link. If your design does
not require CvP, you may select other Hard IP blocks.
6-32
Reset, Status, and Link Training Signals
UG-01145_avst
2015.05.04
Altera Corporation
Interfaces and Signal Descriptions
Send Feedback
- Solutions 1
- Contents 2
- Datasheet 8
- Arria 10 Features 9
- Interface 10
- UG-01145_avst 11
- 2015.05.04 11
- Release Information 13
- Device Family Support 14
- Configurations 14
- Altera FPGA 15
- Debug Features 17
- IP Core Verification 18
- Recommended Speed Grades 18
- Qsys Design Flow 21
- Generating the Testbench 22
- Simulating the Example Design 22
- Directory Description 23
- Time TLP Type Payload 23
- TLP Header 23
- Modifying the Example Design 26
- Component 27
- File Name Description 28
- Subscribe 31
- 2014.08.18 32
- Generating the Qsys System 33
- Parameter Value 34
- Parameter Settings 44
- Parameter Value Description 45
- Device Capabilities 52
- Error Reporting 53
- Link Capabilities 54
- MSI and MSI-X Capabilities 55
- Slot Capabilities 56
- Power Management 57
- PHY Characteristics 58
- Avalon‑ST RX Interface 68
- Packet TLP 73
- Aligned Addresses 77
- Avalon-ST TX Interface 82
- Single Packet Per Cycle 95
- Data 0 Header 2 96
- Clock Signals 97
- Signal Direction Description 100
- Related Information 101
- ECRC Forwarding 102
- Error Signals 102
- Interrupts for Endpoints 103
- Interrupts for Root Ports 104
- Completion Side Band Signals 104
- Signal Directi 105
- Description 105
- Parity Signals 107
- LMI Signals 108
- Altera Corporation 112
- Send Feedback 112
- D E F 0 1 2 3 113
- Field and Bit Map 117
- 0134678951 117
- Bit(s) Field Description 118
- Power Management Signals 120
- 15 011623 8 2791213142431 121
- Bits Field Description 122
- Serial Data Signals 123
- PIPE Interface Signals 123
- Test Signals 128
- Registers 129
- Altera-Defined VSEC Registers 136
- CvP Registers 137
- Bits Register Description 141
- Arria 10 Reset and Clocks 144
- Clock Domains 147
- Clock Summary 149
- Interrupts 150
- MSI Interrupts 151
- Allocated 152
- Implementing MSI-X Interrupts 153
- Legacy Interrupts 155
- Error Handling 157
- Physical Layer Errors 158
- Data Link Layer Errors 158
- Transaction Layer Errors 159
- Error Type Description 160
- Status Bit Conditions 163
- IP Core Architecture 165
- Hard IP for PCI Express 166
- Top-Level Interfaces 167
- Clocks and Reset 168
- Hard IP Reconfiguration 168
- Transaction Layer 169
- Configuration Space 170
- (Soft Logic) 172
- Data Link Layer 174
- Physical Layer 176
- TX Packets 177
- Supported Message Types 179
- Power Management Messages 180
- Error Signaling Messages 181
- Locked Transaction Message 182
- Slot Power Limit Message 182
- Vendor-Defined Messages 182
- Hot Plug Messages 183
- Receive Buffer Reordering 185
- Using Relaxed Ordering 187
- Throughput Optimization 190
- Throughput of Posted Writes 192
- Design Implementation 194
- SDC Timing Constraints 195
- Optional Features 196
- ECRC on the RX Path 197
- ECRC on the TX Path 198
- TLP on Applica‐ 199
- TLP on Link Comments 199
- Testbench and Design Example 201
- Root Port Testbench 203
- Chaining DMA Design Examples 204
- Root Complex 205
- Chaining DMA 205
- Hard IP for 205
- PCI Express 205
- BAR/Address Map 208
- Memory BAR Mapping 209
- Bit Field Description 210
- Addr Register Name 211
- Byte Address 213
- Offset to Base 213
- Descriptor Type Description 213
- Test Driver Module 215
- DMA Write Cycles 216
- DMA Read Cycles 218
- Root Port Design Example 220
- Root Port 221
- Variation 221
- (variation_name.v) 221
- Root Port BFM 222
- BFM Configuration Procedures 223
- BFM Request Interface 223
- BFM Memory Map 224
- Offset (Bytes) Description 226
- BFM Procedures and Functions 230
- Location altpcietb_bfm_rdwr.v 231
- Shared Memory Constants 239
- Constant Description 240
- Location 245
- Setting Up Simulation 257
- Debugging 259
- Use Third-Party PCIe Analyzer 263
- BIOS Enumeration Issues 263
- Frequently Asked Questions 264
- 7 6 5 4 3 2 1 0 265
- Core Config 8 4 1 265
- Additional Information 267
- Date Version Changes Made 268
- How to Contact Altera 272
- Typographic Conventions 273
- Visual Cue Meaning 274
Manuais e produtos relacionados com Instrumentos de medida Altera Arria 10 Avalon-ST
Instrumentos de medida Altera DDR SDRAM High-Performance Controllers and ALTMEMP Manual do Utilizador
(140 páginas)
(140 páginas)
Instrumentos de medida Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manual do Utilizador
(3 páginas)
(3 páginas)
Instrumentos de medida Altera Nios II Embedded Evaluation Kit Cyclone III Editio Manual do Utilizador
(80 páginas)
(80 páginas)
© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.034 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais