Altera Arria 10 Avalon-ST Manual do Utilizador Página 70
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Signal Direction Description
rx_st_valid Output Clocks rx_st_data into the Application Layer. Deasserts within
2 clocks of rx_st_ready deassertion and reasserts within 2 clocks
of rx_st_ready assertion if more data is available to send.
For 256-bit data, when you turn on Enable multiple packets per
cycle, bit 0 applies to the entire bus rx_st_data[255:0]. Bit 1 is
not used.
rx_st_err[<n>-1:0]
Output Indicates that there is an uncorrectable error correction coding
(ECC) error in the internal RX buffer. Active when ECC is
enabled. ECC is automatically enabled by the Quartus II
assembler. ECC corrects single-bit errors and detects double-bit
errors on a per byte basis.
When an uncorrectable ECC error is detected, rx_st_err is
asserted for at least 1 cycle while rx_st_valid is asserted.
For 256-bit data, when you turn on Enable multiple packets per
cycle, bit 0 applies to the entire bus rx_st_data[255:0]. Bit 1 is
not used.
Altera recommends resetting the Arria 10 Hard IP for PCI
Express when an uncorrectable double-bit ECC error is detected.
Attention: If you instantiate this IP core as a separate component from the Quartus II IP Catalog, the
Message pane reports the following warning messages:
pcie_a10.pcie_a10_hip_0.tx.st Interface must have an associated reset
pcie_a10.pcie_a10_hip_0.rx.st Interface must have an associated reset
You can safely ignore these warnings because the IP core has a dedicated hard reset pin that is
not part of the Avalon-ST TX or RX interface.
Related Information
Avalon Interface Specifications.
Avalon‑ST RX Component Specific Signals
Table 6-2: Avalon-ST RX Component Specific Signals
Signal Direction Description
rx_st_mask Input
The Application Layer asserts this signal to tell the Hard IP to
stop sending non-posted requests. This signal can be asserted at
any time. The total number of non-posted requests that can be
transferred to the Application Layer after rx_st_mask is asserted
is not more than 10.
6-4
Avalon‑ST RX Component Specific Signals
UG-01145_avst
2015.05.04
Altera Corporation
Interfaces and Signal Descriptions
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- Solutions 1
- Contents 2
- Datasheet 8
- Arria 10 Features 9
- Interface 10
- UG-01145_avst 11
- 2015.05.04 11
- Release Information 13
- Device Family Support 14
- Configurations 14
- Altera FPGA 15
- Debug Features 17
- IP Core Verification 18
- Recommended Speed Grades 18
- Qsys Design Flow 21
- Generating the Testbench 22
- Simulating the Example Design 22
- Directory Description 23
- Time TLP Type Payload 23
- TLP Header 23
- Modifying the Example Design 26
- Component 27
- File Name Description 28
- Subscribe 31
- 2014.08.18 32
- Generating the Qsys System 33
- Parameter Value 34
- Parameter Settings 44
- Parameter Value Description 45
- Device Capabilities 52
- Error Reporting 53
- Link Capabilities 54
- MSI and MSI-X Capabilities 55
- Slot Capabilities 56
- Power Management 57
- PHY Characteristics 58
- Avalon‑ST RX Interface 68
- Packet TLP 73
- Aligned Addresses 77
- Avalon-ST TX Interface 82
- Single Packet Per Cycle 95
- Data 0 Header 2 96
- Clock Signals 97
- Signal Direction Description 100
- Related Information 101
- ECRC Forwarding 102
- Error Signals 102
- Interrupts for Endpoints 103
- Interrupts for Root Ports 104
- Completion Side Band Signals 104
- Signal Directi 105
- Description 105
- Parity Signals 107
- LMI Signals 108
- Altera Corporation 112
- Send Feedback 112
- D E F 0 1 2 3 113
- Field and Bit Map 117
- 0134678951 117
- Bit(s) Field Description 118
- Power Management Signals 120
- 15 011623 8 2791213142431 121
- Bits Field Description 122
- Serial Data Signals 123
- PIPE Interface Signals 123
- Test Signals 128
- Registers 129
- Altera-Defined VSEC Registers 136
- CvP Registers 137
- Bits Register Description 141
- Arria 10 Reset and Clocks 144
- Clock Domains 147
- Clock Summary 149
- Interrupts 150
- MSI Interrupts 151
- Allocated 152
- Implementing MSI-X Interrupts 153
- Legacy Interrupts 155
- Error Handling 157
- Physical Layer Errors 158
- Data Link Layer Errors 158
- Transaction Layer Errors 159
- Error Type Description 160
- Status Bit Conditions 163
- IP Core Architecture 165
- Hard IP for PCI Express 166
- Top-Level Interfaces 167
- Clocks and Reset 168
- Hard IP Reconfiguration 168
- Transaction Layer 169
- Configuration Space 170
- (Soft Logic) 172
- Data Link Layer 174
- Physical Layer 176
- TX Packets 177
- Supported Message Types 179
- Power Management Messages 180
- Error Signaling Messages 181
- Locked Transaction Message 182
- Slot Power Limit Message 182
- Vendor-Defined Messages 182
- Hot Plug Messages 183
- Receive Buffer Reordering 185
- Using Relaxed Ordering 187
- Throughput Optimization 190
- Throughput of Posted Writes 192
- Design Implementation 194
- SDC Timing Constraints 195
- Optional Features 196
- ECRC on the RX Path 197
- ECRC on the TX Path 198
- TLP on Applica‐ 199
- TLP on Link Comments 199
- Testbench and Design Example 201
- Root Port Testbench 203
- Chaining DMA Design Examples 204
- Root Complex 205
- Chaining DMA 205
- Hard IP for 205
- PCI Express 205
- BAR/Address Map 208
- Memory BAR Mapping 209
- Bit Field Description 210
- Addr Register Name 211
- Byte Address 213
- Offset to Base 213
- Descriptor Type Description 213
- Test Driver Module 215
- DMA Write Cycles 216
- DMA Read Cycles 218
- Root Port Design Example 220
- Root Port 221
- Variation 221
- (variation_name.v) 221
- Root Port BFM 222
- BFM Configuration Procedures 223
- BFM Request Interface 223
- BFM Memory Map 224
- Offset (Bytes) Description 226
- BFM Procedures and Functions 230
- Location altpcietb_bfm_rdwr.v 231
- Shared Memory Constants 239
- Constant Description 240
- Location 245
- Setting Up Simulation 257
- Debugging 259
- Use Third-Party PCIe Analyzer 263
- BIOS Enumeration Issues 263
- Frequently Asked Questions 264
- 7 6 5 4 3 2 1 0 265
- Core Config 8 4 1 265
- Additional Information 267
- Date Version Changes Made 268
- How to Contact Altera 272
- Typographic Conventions 273
- Visual Cue Meaning 274
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