Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manual do Utilizador Página 89
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Name Signal
Direction
Description
rx_inc_fcs_err
Output Asserted for one cycle when a RX packet with FCS errors is received.
Assertion of this signal might be early or delayed compared to
assertion of the dout_fcs_error signal on the RX custom streaming
interface, because the IP core asserts rx_inc_fcs_err when the MAC
sees the FCS error, and asserts dout_fcs_error when it presents the
relevant frame on the custom streaming client interface. Depending on
the filtering settings in the RX_FILTER_CTRL register, the frame might
not appear at all on the client interface.
rx_inc_fragment
Output Asserted for one cycle when a RX frame less than 64 bytes and
reporting a CRC error is received.
rx_inc_jabber
Output Asserted for one cycle when an oversized RX frame reporting a CRC
error is received.
rx_inc_sizeok_
fcserr
Output Asserted for one cycle when a valid RX frame with FCS errors is
received.
Related Information
Statistics Registers on page 3-108
The statistics status bit output vectors are provided whether you select the statistics counters module
option or not. The increment vectors are brought to the top level as output ports and function as input
ports to the control and status registers (CSR).
MAC – PHY XLGMII or CGMII Interface
The PHY side of the MAC implements the XLGMII or CGMII protocol as defined by the IEEE 802.3ba
standard. The standard XLGMII or CGMII implementation consists of 32 bit wide data bus. However, the
Altera implementation uses a wider bus interface in connecting a MAC to the internal PHY. The width of
this interface is 320 bits for the 100GbE IP core and 128 bits for the 40GbE IP core.
Table 3-10: XL/CGMII Permissible Encodings
Lists XL/CGMII permissible encodings. Memorizing a few of the XL/CGMII encodings greatly facilitates
understanding of Ethernet waveforms. The XL/CGMII encodings are backwards compatible with older Ethernet
and have convenient mnemonics. The DATAPATH_OPTION RTL parameter instantiates TX and RX backwards
compatibility and is set by default.
Control Data Description
0 xx Packet data, including preamble and FCS bytes.
1 07 Idle.
1 fb Start of Frame (fb = frame begin).
3-42
MAC – PHY XLGMII or CGMII Interface
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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