Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manual do Utilizador Página 85
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MAC and the XLGMII or CGMII to manage local and remote faults. Link fault signaling on the Ethernet
link is disabled by default but can be enabled by the Enable Link Fault Sequence register. When
enabled, the local RS TX logic can transmit remote fault sequences in case of a local fault and can transmit
IDLE control words in case of a remote fault. An additional configuration register (MAC/RS link fault
sequence configuration) is provided to select the type of information to be transmitted in case of a
local or remote fault. Using the configuration bits, you can send remote fault sequence ordered sets, IDLE
control words, or regular traffic in the case of a local or remote fault.
The RS RX logic sets remote_fault_status or local_fault_status to 1 when the RS RX block receives
remote fault or local fault sequence ordered sets. When valid data is received in more than 127 columns,
the RS RX logic resets the relevant fault status (remote_fault_status or local_fault_status) to 0.
Figure 3-30: Link Fault Signaling Example
Idle
Remote Fault Sequence
Local Fault Status, Remote Fault
Status & Fault Configuration
Normal mii Traffic
mii_d[319:0]
mii_c[39:0]
The IEEE standard specifies RS monitoring of RXC<7:0> and RXD<63:0> for Sequence ordered_sets.
For more information, refer to Figure 81–9—Link Fault Signaling state diagram and Table 81-5—Sequence
ordered_sets in the IEEE 802.3ba 2010 100G Ethernet Standard . The variable link_fault is set to
indicate the value of an RX Sequence ordered_set when four fault_sequences containing the same
fault value are received with fault sequences separated by less than 128 columns and with no intervening
fault_sequences of different fault values. The variable link_fault is set to OK following any interval of
128 columns not containing a remote fault or local fault Sequence ordered_set.
Table 3-8: Signals of the Link Fault Signaling Interface
Signal Name Direction Description
remote_fault_from_
rx
Output Asserted when remote fault is detected in RX MAC. Available in
RX-only variations.
local_fault_from_rx Output Asserted when local fault is detected in RX MAC. Available in RX-
only variations.
remote_fault_to_tx
Input Input to the TX MAC. Asserted when remote fault is detected.
Visible in TX-only variations and used internally in duplex IP core
variations.
local_fault_to_tx
Input Input to the TX MAC. Asserted when local fault is detected.
Visible in TX-only variations and used internally in duplex IP core
variations.
remote_fault_status
Output
Asserted when remote fault is detected in RX MAC in a duplex IP
core variation. In duplex IP core variations, remote_fault_from_
rx is connected internally to remote_fault_to_tx, and this signal
is available externally as remote_fault_status.
3-38
Link Fault Signaling Interface
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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