Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manual do Utilizador Página 43
- Página / 199
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
Generating the 40-100GbE Testbench
A single procedure generates both the testbench and the example project. To generate the testbench and
example project:
1. Follow the steps in Specifying the 40-100GbE IP Core Parameters and Options to parameterize your
IP core.
2. Generate the IP core by clicking Generate.
Note: When prompted at the start of generation, you must turn on Generate example design.
Turning on Generate example design is the only process that generates a functional testbench
and a functional example design.
When the IP core is generated in <working directory>, the testbench and example project are generated
in <working directory>/<IP core variation>/_example/alt_e40_e100.
The directory with the testbench and example project has two subdirectories:
• example, which contains the example design project
• example_testbench, which contains the demonstration testbench
Simulating with the Modelsim Simulator
To run the simulation in the ModelSim simulation tool, follow these steps:
1. Change directory to the <variation_name> _example/alt_e40_e100/example_testbench directory.
2. In the command line, type: vsim -c -do run_vsim.do
The example testbench will run and pass.
Simulating with the NCSim Simulator
To run the simulation in the NCSim simulation tool, follow these steps:
1. Change directory to the <variation_name> _example/alt_e40_e100/example_testbench directory.
2. In the command line, type: sh run_ncsim.sh
The example testbench will run and pass.
Simulating with the VCS Simulator
To run the simulation in the VCS simulation tool, follow these steps:
1. Change directory to the <variation_name> _example/alt_e40_e100/example_testbench directory.
2. In the command line, type: sh run_vcs.sh
The example testbench will run and pass.
Testbench Output Example: 40GbE IP Core with Adapters
This section shows successful simulation using the 40GbE IP core with adapters testbench (alt_40gbe_
tb.sv). The testbench connects the Ethernet TX lanes to the Ethernet RX lanes, so that the IP core is in an
external loopback configuration. In simulation, the testbench resets the IP core and waits for lane
alignment and deskew to complete successfully. The packet generator sends ten packets on the Ethernet
TX lanes and the packet checker checks the packets when the IP core receives them on the Ethernet RX
lanes.
UG-01088
2014.12.15
Generating the 40-100GbE Testbench
2-21
Getting Started
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
Manuais e produtos relacionados com Instrumentos de medida Altera 40-Gbps Ethernet MAC and PHY MegaCore Function
(39 páginas)© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.024 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais