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Word
Addr
Bit R/W Name Description
0xB4 31:0 RSC FEC Uncorrected
Blocks
Counts the number of uncorrectable FEC blocks. Resets to 0
when read. Otherwise, it holds at the maximum count and
does not roll over. Refer to Clause 74.8.4.1 of IEEE 802.3ap-
2000 for details.
0xC0
0 RW AN enable When set to 1, enables Auto-Negotiation function. The
default value is 1. For additional information, refer to bit
7.0.12 in Clause 73.8 Management Register Requirements, of
IEEE 802.3ap
-
2007.
1 RW AN base pages
ctrl
When set to 1, the user base pages are enabled. You can send
any arbitrary data via the user base page low/high bits. When
set to 0, the user base pages are disabled and the state
machine generates the base pages to send.
2 RW AN next pages
ctrl
When set to 1, the user next pages are enabled. You can send
any arbitrary data via the user next page low/high bits. When
set to 0, the user next pages are disabled. The state machine
generates the null message to send as next pages.
3 R Local device
remote fault
When set to 1, the local device signals Remote Faults in the
Auto-Negotiation pages. When set to 0 a fault has not
occurred.
4 RW Force TX nonce
value
When set to 1, forces the TX none value to support some
UNH-IOL testing modes. When set to 0, operates normally.
5 RW Override AN When set to 1, the override settings defined by the AN_TECH,
AN_FEC and AN_PAUSE registers take effect.
0xC1
0 RW Reset AN When set to 1, resets all the 10GBASE-KR Auto-Negotiation
state machines. This bit is self-clearing.
4 RW Restart AN TX SM When set to 1, restarts the 10GBASE-KR TX state machine.
This bit self clears. This bit is active only when the TX state
machine is in the AN state. For more information, refer to bit
7.0.9 in Clause 73.8 Management Register Requirements of
IEEE 802.3ap
-
2007.
8 RW AN Next Page When asserted, new next page info is ready to send. The data
is in the XNP TX registers. When 0, the TX interface sends
null pages. This bit self clears. Next Page (NP) is encoded in
bit D15 of Link Codeword. For more information, refer to
Clause 73.6.9 and bit 7.16.15 of Clause 45.2.7.6 of IEEE
802.3ap
-
2007.
0xC2
1 RO AN page received When set to 1, a page has been received. When 0, a page has
not been received. The current value clears when the register
is read. For more information, refer to bit 7.1.6 in Clause 73.8
of IEEE 802.3ap
-
2007.
2 RO AN Complete When asserted, Auto-Negotiation has completed. When 0,
Auto-Negotiation is in progress. For more information, refer
to bit 7.1.5 in Clause 73.8 of IEEE 802.3ap
-
2007.
C-4
10GBASE-KR PHY Register Definitions
UG-01088
2014.12.15
Altera Corporation
10GBASE-KR Registers
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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