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Chapter 10: Transceiver Reconfiguration Controller 10–25
Streamer Module
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Mode 1 Avalon-MM Direct Writes for Reconfiguration
You specify this mode by writing a value of 2'b01 into bits 2 and 3 of the
control and
status
register, as indicated in Table 10–22 on page 10–23. In this mode, you can write
directly to transceiver PHY IP core registers to perform reconfiguration. Refer to
“Direct Write Reconfiguration” on page 10–29 for an example of an update using
mode 1. In mode 1, you can selectively reconfigure portions of the transceiver PHY IP
core. Unlike mode 0, mode 1 allows you to write only the data required for a
reconfiguration.
Stratix V MIF
The Stratix V MIF stores the reconfiguration data for the transceiver PHY IP cores. The
Quartus II software automatically generates MIFs after each successful compilation.
MIFs are stored in the reconfig_mif folder of the project's working directly. This
folder stores all MIFs associated with the compiled project for each transceiver PHY
IP core instance in the design. The parameter settings of PHY IP core instance reflect
the currently specified MIF. You can store the MIF in an on-chip ROM or any other
type of memory. This memory must connect to the MIF reconfiguration management
interface.
Example 10–1 shows file names for the .mif files for a design with two channels. This
design example includes two transceiver PHY IP core instances running at different
data rates. Both transceiver PHY IP core instances have two TX PLLs specified to
support both 1 Gbps and 2.5 Gbps data rates. The Quartus II software generates two
TX PLL .mif files for each PLL. The difference between the .mif files is the PLL
reference clock specified. To dynamically reconfigure the channel from the initially
specified data rate to a new data rate, you can use the MIF streaming function to load
the other .mif.
1 When reconfiguration is limited to a few settings, you can create a partial .mif that
only includes the settings that must be updated.
MIF Format
The Stratix-V MIF file is organized into records where each record contains the
information necessary to carry out the reconfiguration process. There are two types of
records: non-data records and data records. A MIF can contain a variable number of
records, depending on the target transceiver channel. Both data records and non-data
records are 16-bits long.
For both record types the high-order 5 bits represent the
length
field. A
length
field
of 5’b0, indicates a non-data record which contains an opcode. A length field that is
not zero indicates a data record.
Example 10–1. Quartus II Generated MIF Files
<project_dir>/reconfig_mif/inst0_1g_channel.mif
<project_dir>/reconfig_mif/inst0_1g_txpll0.mif
<project_dir>/reconfig_mif/inst0_1g_txpll1.mif
<project_dir>/reconfig_mif/inst0_2p5g_channel.mif
<project_dir>/reconfig_mif/inst0_2p5g_txpll0.mif
<project_dir>/reconfig_mif/inst0_2p5g_txpll1.mif
- User Guide 1
- Contents 3
- Chapter 7. Custom PHY IP Core 5
- Contents vi 6
- 1. Introduction 9
- Stratix V Device 10
- Reset Controller 11
- Avalon-MM PHY Management 11
- 1–4 Chapter 1: Introduction 12
- Unsupported Features 13
- 1–6 Chapter 1: Introduction 14
- 2. Getting Started 15
- Note to Figure2–2: 16
- Simulate the IP Core 18
- 3. 10GBASE-R PHY IP Core 19
- Release Information 20
- Note to Table 3–1: 21
- Stratix IV Devices 23
- Stratix V Devices 24
- SDR XGMII TX Interface 30
- Note to Table 3–9: 30
- SDR XGMII RX Interface 31
- Note to Table 3–11: 31
- Status Interface 32
- Clocks, Reset, and Powerdown 32
- Serial Interface 35
- Note to Table 3–15: 35
- TimeQuest Timing Constraints 40
- Note to Figure4–1: 43
- Note to Table 4–1: 44
- Advanced Options 51
- Configurations 52
- PMA Channel Controller 58
- Stratix IV GX Devices 65
- 5. Interlaken PHY IP Core 67
- Analog Settings 70
- Note to Figure5–2: 74
- Avalon-ST TX Interface 75
- Avalon-ST RX Interface 76
- PLL Interface 78
- TX and RX Serial Interface 78
- Optional Clocks for Deskew 78
- Transceiver Reconfiguration 81
- General Options 84
- Note to Figure6–2: 90
- PIPE Interface 92
- Note to Table 6–8: 93
- Transceiver Serial Interface 94
- Registers 95
- 7. Custom PHY IP Core 101
- Device Family Support 102
- Parameter Settings 103
- Word Alignment 106
- Rate Match FIFO 107
- 8B/10B Encoder and Decoder 108
- Byte Ordering 108
- PLL Reconfiguration 109
- Analog Options 110
- Presets for Ethernet 114
- Interfaces 115
- Note to Figure7–2: 116
- Clock Interface 118
- Status Signals (Optional) 118
- Note to Table 7–17: 119
- Register Interface 120
- Register Descriptions 121
- Dynamic Reconfiguration 124
- 8. Low Latency PHY IP Core 125
- Note to Table 8–4: 129
- Note to Table 8–5: 130
- Serial Data Interface 137
- Optional Status Interface 138
- PMA and Light-Weight PCS 139
- Arria V or Stratix V FPGA 143
- Auto-Negotiation 144
- Delay Estimation Logic 145
- Note to Figure9–2: 145
- Delay Numbers 146
- Note to Table 9–4: 147
- Additional Options 150
- TX and RX Status Signals 159
- Deterministic PHY IP Core 161
- Controller 167
- Note to Figure10–1: 169
- Note to Table 10–6: 174
- Embedded 175
- Offset Cancellation 176
- Duty Cycle Calibration 176
- PMA Analog Controls 177
- Pre-CDR Reverse Serial 178
- Loopback 178
- Post-CDR Reverse Serial 178
- ATX PLL Calibration 183
- Channel Reconfiguration 187
- Streamer Module 188
- Stratix V MIF 191
- Register-Based Write 193
- Register-Based Read 193
- Direct Write Reconfiguration 195
- Figure 10–6. Sample MIF 196
- Example 10–5. (continued) 197
- Notes to Figure 10–14: 205
- Transceiver 206
- XAUI PHY 209
- Port Differences 210
- Note to Table 11–3: 212
- Note to Table 11–5: 215
- Custom PHY 216
- Note to Table 11–6: 217
- Note to Table 11–7: 218
- Additional Information 219
- Revision History 220
- Note to Table: 228
- Typographic Conventions 229
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