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9–24 Chapter 9: Deterministic Latency PHY IP Core
Simulation Files and Example Testbench
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Figure 9–5 shows the placement of transceiver banks in Arria V devices and indicates
the channels that are not available.
Simulation Files and Example Testbench
Refer to “Running a Simulation Testbench” on page 1–4 for a description of the
directories and files that the Quartus II software creates automatically when you
generate your Deterministic Latency PHY IP core.
This chapter provides additional information about the document and Altera.
Figure 9–5. Channel Placement and Available Channels in Arria V Devices
GXB_R0
GXB_R1
GXB_L0
GXB_L1
GXB_R2GXB_L2
Devices Available
Number of Channels Per Bank
Transceiver Bank Names
5AGXB5KF40
5AGXB7KF40
5AGXA5HF35
5AGXA7HF35
5AGXB1HF35
5AGXB1HF40
5AGXB3HF35
5AGXB3HF40
5AGXB5HF35
5AGXB7HF35
5AGXA1EF31
5AGXA3EF31
PCIe Hard IP
PCIe Hard IP
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
Ch 0
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
Ch 0
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 5
Ch 4
Ch 3
Ch 2
Ch 1
Ch 0
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Not Available for
Deterministic
Protocols
Not Available for
Deterministic
Protocols
- User Guide 1
- Contents 3
- Chapter 7. Custom PHY IP Core 5
- Contents vi 6
- 1. Introduction 9
- Stratix V Device 10
- Reset Controller 11
- Avalon-MM PHY Management 11
- 1–4 Chapter 1: Introduction 12
- Unsupported Features 13
- 1–6 Chapter 1: Introduction 14
- 2. Getting Started 15
- Note to Figure2–2: 16
- Simulate the IP Core 18
- 3. 10GBASE-R PHY IP Core 19
- Release Information 20
- Note to Table 3–1: 21
- Stratix IV Devices 23
- Stratix V Devices 24
- SDR XGMII TX Interface 30
- Note to Table 3–9: 30
- SDR XGMII RX Interface 31
- Note to Table 3–11: 31
- Status Interface 32
- Clocks, Reset, and Powerdown 32
- Serial Interface 35
- Note to Table 3–15: 35
- TimeQuest Timing Constraints 40
- Note to Figure4–1: 43
- Note to Table 4–1: 44
- Advanced Options 51
- Configurations 52
- PMA Channel Controller 58
- Stratix IV GX Devices 65
- 5. Interlaken PHY IP Core 67
- Analog Settings 70
- Note to Figure5–2: 74
- Avalon-ST TX Interface 75
- Avalon-ST RX Interface 76
- PLL Interface 78
- TX and RX Serial Interface 78
- Optional Clocks for Deskew 78
- Transceiver Reconfiguration 81
- General Options 84
- Note to Figure6–2: 90
- PIPE Interface 92
- Note to Table 6–8: 93
- Transceiver Serial Interface 94
- Registers 95
- 7. Custom PHY IP Core 101
- Device Family Support 102
- Parameter Settings 103
- Word Alignment 106
- Rate Match FIFO 107
- 8B/10B Encoder and Decoder 108
- Byte Ordering 108
- PLL Reconfiguration 109
- Analog Options 110
- Presets for Ethernet 114
- Interfaces 115
- Note to Figure7–2: 116
- Clock Interface 118
- Status Signals (Optional) 118
- Note to Table 7–17: 119
- Register Interface 120
- Register Descriptions 121
- Dynamic Reconfiguration 124
- 8. Low Latency PHY IP Core 125
- Note to Table 8–4: 129
- Note to Table 8–5: 130
- Serial Data Interface 137
- Optional Status Interface 138
- PMA and Light-Weight PCS 139
- Arria V or Stratix V FPGA 143
- Auto-Negotiation 144
- Delay Estimation Logic 145
- Note to Figure9–2: 145
- Delay Numbers 146
- Note to Table 9–4: 147
- Additional Options 150
- TX and RX Status Signals 159
- Deterministic PHY IP Core 161
- Controller 167
- Note to Figure10–1: 169
- Note to Table 10–6: 174
- Embedded 175
- Offset Cancellation 176
- Duty Cycle Calibration 176
- PMA Analog Controls 177
- Pre-CDR Reverse Serial 178
- Loopback 178
- Post-CDR Reverse Serial 178
- ATX PLL Calibration 183
- Channel Reconfiguration 187
- Streamer Module 188
- Stratix V MIF 191
- Register-Based Write 193
- Register-Based Read 193
- Direct Write Reconfiguration 195
- Figure 10–6. Sample MIF 196
- Example 10–5. (continued) 197
- Notes to Figure 10–14: 205
- Transceiver 206
- XAUI PHY 209
- Port Differences 210
- Note to Table 11–3: 212
- Note to Table 11–5: 215
- Custom PHY 216
- Note to Table 11–6: 217
- Note to Table 11–7: 218
- Additional Information 219
- Revision History 220
- Note to Table: 228
- Typographic Conventions 229
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