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8–14 Chapter 8: Low Latency PHY IP Core
Interfaces
Altera Transceiver PHY IP Core March 2012 Altera Corporation
User Guide
Optional Status Interface
Table 8–11 describes the signals that comprise the optional status interface.
Clock Interface
Table 8–12 describes reference clock for the Low Latency PHY. The input reference
clock,
pll_ref_clk
, drives a PLL inside the PHY-layer block, and a PLL output clock,
rx_clkout
is used for all data, command, and status inputs and outputs.
Reset Control and Status (Optional)
Table 8–13 describes the signals in the optional reset control and status interface.
These signals are available if you do not enable the embedded reset controller. For
more information including timing diagrams, refer to Transceiver Reset Control in
Stratix V Devices in volume 3 of the Stratix V Device Handbook.
Table 8–11. Optional Status Interface
Signal Name Direction Description
rx_is_lockedtodata[<n>-1:0]
Output
When asserted, indicates that the RX CDR is locked to
incoming data. This signal is optional. If latency is not critical,
you can read the value of this signal from the
Rx_is_lockedtodata
register.
rx_is_lockedtoref[<n>-1:0]
Output
When asserted, indicates that the RX CDR is locked to the input
reference clock. This signal is optional. When the RX CDR is
locked to data, you can ignore transitions on this signal. If
latency is not critical, you can read the value of this signal from
the rx_is_lockedtoref register.
pll_locked[<n>-1:0]
Output
When asserted, indicates that the TX PLL is locked to the input
reference clock. This signal is asynchronous.
tx_bitslip[<n>-1:0]
Output
When set, the data sent to the PMA is slipped. The maximum
number of bits that can be slipped is equal to the value selected
in the serialization factor field - 1 or <d> -1.
Table 8–12. Clock Signals
Signal Name Direction Description
tx_coreclkin[<n>-1:0]
Input This is an optional clock to drive the write side of the TX FIFO.
rx_coreclkin[<n>-1:0]
Input This is an optional clock to drive the read side of the RX FIFO.
pll_ref_clk
Input
Reference clock for the PHY PLLs. The frequency range is
60–700 MHz.
Table 8–13. Avalon-ST RX Interface (Part 1 of 2)
Signal Name Direction Description
pll_powerdown
Input When asserted, resets the TX PLL.
tx_digitalreset[<n>-1:0]
Input When asserted, reset all blocks in the TX PCS.
tx_analogreset[<n>-1:0]
Input When asserted, resets all blocks in the TX PMA.
tx_cal_busy[<n>-1:0]
Output
When asserted, indicates that the TX channel is being calibrated. You
must hold the channel in reset until calibration completes.
rx_digitalreset[<n>-1:0]
Input When asserted, resets the RX PCS.
- User Guide 1
- Contents 3
- Chapter 7. Custom PHY IP Core 5
- Contents vi 6
- 1. Introduction 9
- Stratix V Device 10
- Reset Controller 11
- Avalon-MM PHY Management 11
- 1–4 Chapter 1: Introduction 12
- Unsupported Features 13
- 1–6 Chapter 1: Introduction 14
- 2. Getting Started 15
- Note to Figure2–2: 16
- Simulate the IP Core 18
- 3. 10GBASE-R PHY IP Core 19
- Release Information 20
- Note to Table 3–1: 21
- Stratix IV Devices 23
- Stratix V Devices 24
- SDR XGMII TX Interface 30
- Note to Table 3–9: 30
- SDR XGMII RX Interface 31
- Note to Table 3–11: 31
- Status Interface 32
- Clocks, Reset, and Powerdown 32
- Serial Interface 35
- Note to Table 3–15: 35
- TimeQuest Timing Constraints 40
- Note to Figure4–1: 43
- Note to Table 4–1: 44
- Advanced Options 51
- Configurations 52
- PMA Channel Controller 58
- Stratix IV GX Devices 65
- 5. Interlaken PHY IP Core 67
- Analog Settings 70
- Note to Figure5–2: 74
- Avalon-ST TX Interface 75
- Avalon-ST RX Interface 76
- PLL Interface 78
- TX and RX Serial Interface 78
- Optional Clocks for Deskew 78
- Transceiver Reconfiguration 81
- General Options 84
- Note to Figure6–2: 90
- PIPE Interface 92
- Note to Table 6–8: 93
- Transceiver Serial Interface 94
- Registers 95
- 7. Custom PHY IP Core 101
- Device Family Support 102
- Parameter Settings 103
- Word Alignment 106
- Rate Match FIFO 107
- 8B/10B Encoder and Decoder 108
- Byte Ordering 108
- PLL Reconfiguration 109
- Analog Options 110
- Presets for Ethernet 114
- Interfaces 115
- Note to Figure7–2: 116
- Clock Interface 118
- Status Signals (Optional) 118
- Note to Table 7–17: 119
- Register Interface 120
- Register Descriptions 121
- Dynamic Reconfiguration 124
- 8. Low Latency PHY IP Core 125
- Note to Table 8–4: 129
- Note to Table 8–5: 130
- Serial Data Interface 137
- Optional Status Interface 138
- PMA and Light-Weight PCS 139
- Arria V or Stratix V FPGA 143
- Auto-Negotiation 144
- Delay Estimation Logic 145
- Note to Figure9–2: 145
- Delay Numbers 146
- Note to Table 9–4: 147
- Additional Options 150
- TX and RX Status Signals 159
- Deterministic PHY IP Core 161
- Controller 167
- Note to Figure10–1: 169
- Note to Table 10–6: 174
- Embedded 175
- Offset Cancellation 176
- Duty Cycle Calibration 176
- PMA Analog Controls 177
- Pre-CDR Reverse Serial 178
- Loopback 178
- Post-CDR Reverse Serial 178
- ATX PLL Calibration 183
- Channel Reconfiguration 187
- Streamer Module 188
- Stratix V MIF 191
- Register-Based Write 193
- Register-Based Read 193
- Direct Write Reconfiguration 195
- Figure 10–6. Sample MIF 196
- Example 10–5. (continued) 197
- Notes to Figure 10–14: 205
- Transceiver 206
- XAUI PHY 209
- Port Differences 210
- Note to Table 11–3: 212
- Note to Table 11–5: 215
- Custom PHY 216
- Note to Table 11–6: 217
- Note to Table 11–7: 218
- Additional Information 219
- Revision History 220
- Note to Table: 228
- Typographic Conventions 229
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